CD4011UB

現行

4 通道、2 輸入、3-V 至 18-V NAND 閘

立即訂購

產品規格表

document-pdfAcrobat CD4011UB TYPES datasheet (Rev. D) (英文)

CD4011UB

現行

產品規格表

立即訂購

產品詳細資料

Technology family

CD4000

Number of channels

4

Inputs per channel

2

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Input type

Standard CMOS

Output type

Push-Pull

Features

High speed (tpd 10-50ns)

Data rate (max) (Mbps)

8

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

CD4000

Number of channels

4

Inputs per channel

2

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Input type

Standard CMOS

Output type

Push-Pull

Features

High speed (tpd 10-50ns)

Data rate (max) (Mbps)

8

Rating

Catalog

Operating temperature range (°C)

-55 to 125

SOIC (D)

14

51.9 mm² (8.65 mm × 6 mm)

PDIP (N)

14

181.42 mm² (19.3 mm × 9.4 mm)

SOP (NS)

14

79.56 mm² (10.2 mm × 7.8 mm)

TSSOP (PW)

14

32 mm² (5 mm × 6.4 mm)

Propagation delay time = 30 ns (typ). at C_L = 50 pF, V_DD = 10 V
Standardized symmetrical output characteristics
100% tested for quiescent current at 20V
Maximum input current of 1 µA at 18 V over full package temperature range; 100nA at 18 V and 25°C
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

Propagation delay time = 30 ns (typ). at C_L = 50 pF, V_DD = 10 V
Standardized symmetrical output characteristics
100% tested for quiescent current at 20V
Maximum input current of 1 µA at 18 V over full package temperature range; 100nA at 18 V and 25°C
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

CD4011UB quad 2-input NAND gate provides the system designer with direct implementation of the NAND function and supplements the existing family of CMOS gates.

The CD4011UB types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline package (M, MT, M96, NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4011UB quad 2-input NAND gate provides the system designer with direct implementation of the NAND function and supplements the existing family of CMOS gates.

The CD4011UB types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline package (M, MT, M96, NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

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重要文件	類型	標題	格式選項	下載最新的英文版本		日期
*	資料表	CD4011UB TYPES datasheet (Rev. D)				2003/8/21

CD4011UB

4 通道、2 輸入、3-V 至 18-V NAND 閘

CD4011UB

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