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JK 正反器

CD4027B

現行

CMOS 雙路 J-K 主-從正反器

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產品規格表

CD4027B

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 2 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type TTL Output type Push-Pull Clock frequency (MHz) 12 Supply current (max) (µA) 600 IOL (max) (mA) 1.5 IOH (max) (mA) -1.5 Features Balanced outputs, Clear, Positive edge triggered, Positive input clamp diode, Preset, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Catalog
Number of channels 2 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type TTL Output type Push-Pull Clock frequency (MHz) 12 Supply current (max) (µA) 600 IOL (max) (mA) 1.5 IOH (max) (mA) -1.5 Features Balanced outputs, Clear, Positive edge triggered, Positive input clamp diode, Preset, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Catalog
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6 SOP (NS) 16 79.56 mm² 10.2 x 7.8 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Set-reset capability
  • Static flip-flop operation – retains state indefinitely with clock level either high or low
  • Medium speed operation – 16 MHz (typical) clock toggle rate at 10 V
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package-temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • 5 V, 10 V, and 15 V parametric ratings
  • Meets all requirements of JEDEC tentative standard No. 138, standard specifications for description of ’B’ series CMOS devices
  • Set-reset capability
  • Static flip-flop operation – retains state indefinitely with clock level either high or low
  • Medium speed operation – 16 MHz (typical) clock toggle rate at 10 V
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package-temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • 5 V, 10 V, and 15 V parametric ratings
  • Meets all requirements of JEDEC tentative standard No. 138, standard specifications for description of ’B’ series CMOS devices

CD4027B is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K flip flops. Each flip-flop has provisions for individual J, K, Set, Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatibile operation with the RCA-CD4013B dual D-type flip-flop.

The CD4027B is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop; changes in the flip-flop state are synchronous with the postitive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high level signal is present at either the Set or Reset input.

The CD4027B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffice), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4027B is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K flip flops. Each flip-flop has provisions for individual J, K, Set, Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatibile operation with the RCA-CD4013B dual D-type flip-flop.

The CD4027B is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop; changes in the flip-flop state are synchronous with the postitive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high level signal is present at either the Set or Reset input.

The CD4027B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffice), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
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類型 標題 日期
* Data sheet CD4027B CMOS Dual J-K Flip Flop datasheet (Rev. D) PDF | HTML 2021年 7月 14日

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

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