CD4046B-MIL
- Very low power consumption:
70 µW (typ.) at VCO fo = 10 kHz, VDD = 5 V - Operating frequency range up to 1.4 MHz (typ.) at VDD = 10 V, RI = 5 k
- Low frequency drift: 0.04%/°C (typ.) at VDD = 10 V
- Choice of two phase comparators:
- Exclusive-OR network (I)
- Edge-controlled memory network with phase-pulse output for lock indication (II)
- High VCO linearity: <1% (typ.) at VDD = 10 V
- VCO inhibit control for ON-OFF keying and ultra-low standby power consumption
- Source-follower output of VCO control input (Demod. output)
- Zener diode to assist supply regulation
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications
- FM demodulator and modulator
- Frequency synthesis and multiplication
- Frequency discriminator
- Data synchronization
- Voltage-to-frequency conversion
- Tone decoding
- FSK - Modems
- Signal conditioning
- (See ICAN-6101) "RCA COS/MOS Phase-Locked Loop - A Versatile Building Block for Micropower Digital and Analog Applications"
CD4046B CMOS Micropower Phase-Locked Loop (PLL) consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input. A 5.2-V zener diode is provided for supply regulation if necessary.
The CD4046B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
技術文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 2
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CD4046B TYPES datasheet (Rev. B) | 2003/6/27 | |||
| * | SMD | CD4046B-MIL SMD 5962-94664 | 2016/6/21 |