CD4060B
- 12 MHz clock rate at 15 V
- Common reset
- Fully static operation
- Buffered inputs and outputs
- Schmitt trigger input-pulse line
- 100% tested for quiescent current at 20 V
- Standardized, symmetrical output characteristics
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices’
- Oscillator Features:
- All active components on chip
- RC or crystal oscillator configuration
- RC oscillator frequency of 690 kHz min. at 15 V
- Applications
- Control counters
- Timers
- Frequency dividers
- Time-delay circuits
CD4060B consists of an oscillator section and 14 ripple-carry binary counter stages.
The oscillator configuration allows design of either RC or crystal oscillator circuits.
A RESET input is provided which resets the counter to the all-O's state and disables the oscillator.
A high level on the RESET line accomplishes the reset function. All counter stages are master-slave flip-flops.
The state of the counter is advanced one step in binary order on the negative transition of
O).
All inputs and outputs are fully buffered. Schmitt trigger action on the input-pulse line permits unlimited input-pulse
rise and fall times.
The CD4060B-series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CD4060B Types datasheet (Rev. C) | 2003年 10月 14日 | |
| Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
| User guide | Signal Switch Data Book (Rev. A) | 2003年 11月 14日 | ||
| Application note | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | 2001年 12月 3日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| PDIP (N) | 16 | Ultra Librarian |
| SOIC (D) | 16 | Ultra Librarian |
| SOP (NS) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點