CD4070B

現行

4 通道、2 輸入、3-V 至 18-V XOR (exclusive OR) 閘

立即訂購

產品規格表

document-pdfAcrobat CD4070B, CD4077B datasheet (Rev. E) (英文)

CD4070B

現行

產品規格表

立即訂購

產品詳細資料

Technology family

CD4000

Number of channels

Inputs per channel

IOL (max) (mA)

6.8

Input type

Standard CMOS

IOH (max) (mA)

-6.8

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

CD4000

Number of channels

Inputs per channel

IOL (max) (mA)

6.8

Input type

Standard CMOS

IOH (max) (mA)

-6.8

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

Rating

Catalog

Operating temperature range (°C)

-55 to 125

PDIP (N)

181.42 mm² (19.3 mm × 9.4 mm)

SOP (NS)

79.56 mm² (10.2 mm × 7.8 mm)

SOIC (D)

51.9 mm² (8.65 mm × 6 mm)

TSSOP (PW)

32 mm² (5 mm × 6.4 mm)

High-Voltage Types (20V Rating)
CD4070B - Quad Exclusive-OR Gate
CD4077B - Quad Exclusive-NOR Gate
Medium Speed Operation
- t_PHL, t_PLH = 65ns (Typ) at V_DD = 10V, C_L = 50pF
100% Tested for Quiescent Current at 20V
Standardized Symmetrical Output Characteristics
5V, 10V and 15V Parametric Ratings
Maximum Input Current of 1µA at 18V Over Full Package Temperature Range
- 100nA at 18V and 25°C
Noise Margin (Over Full Package Temperature Range)
- 1V at V_DD = 5V, 2V at V_DD = 10V, 2.5V at V_DD = 15V
Meets All Requirements of JEDEC Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices
Applications
- Logical Comparators
- Adders/Subtractors
- Parity Generators and Checkers

Data sheet acquired from Harris Semiconductor

High-Voltage Types (20V Rating)
CD4070B - Quad Exclusive-OR Gate
CD4077B - Quad Exclusive-NOR Gate
Medium Speed Operation
- t_PHL, t_PLH = 65ns (Typ) at V_DD = 10V, C_L = 50pF
100% Tested for Quiescent Current at 20V
Standardized Symmetrical Output Characteristics
5V, 10V and 15V Parametric Ratings
Maximum Input Current of 1µA at 18V Over Full Package Temperature Range
- 100nA at 18V and 25°C
Noise Margin (Over Full Package Temperature Range)
- 1V at V_DD = 5V, 2V at V_DD = 10V, 2.5V at V_DD = 15V
Meets All Requirements of JEDEC Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices
Applications
- Logical Comparators
- Adders/Subtractors
- Parity Generators and Checkers

Data sheet acquired from Harris Semiconductor

The Harris CD4070B contains four independent Exclusive-OR gates. The Harris CD4077B contains four independent Exclusive-NOR gates.

The CD4070B and CD4077B provide the system designer with a means for direct implementation of the Exclusive-OR and Exclusive-NOR functions, respectively.

The Harris CD4070B contains four independent Exclusive-OR gates. The Harris CD4077B contains four independent Exclusive-NOR gates.

The CD4070B and CD4077B provide the system designer with a means for direct implementation of the Exclusive-OR and Exclusive-NOR functions, respectively.

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