CD54ACT174

Name: CD54ACT174
Brand: TI
SKU: CD54ACT174
Price: 10.076 USD

現行

具有重設功能的六路 D 型正反器

立即訂購

產品規格表

document-pdfAcrobat CDx4ACT174 Hex D-Type Flip-Flops with Clear datasheet (Rev. A) (英文) PDF | HTML

CD54ACT174

現行

產品規格表

立即訂購

產品詳細資料

Number of channels

Technology family

ACT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

IOL (max) (mA)

IOH (max) (mA)

-24

Supply current (max) (µA)

160

Features

Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-55 to 125

Rating

Military

Number of channels

Technology family

ACT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

IOL (max) (mA)

IOH (max) (mA)

-24

Supply current (max) (µA)

160

Features

Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-55 to 125

Rating

Military

CDIP (J)

135.3552 mm² 19.56 x 6.92

Inputs are TTL-voltage compatible
Contain six flip-flops with single-rail outputs
Buffered inputs
Speed of bipolar F, AS, and S, with significantly reduced power consumption
Balanced propagation delays
±24mA output drive current
- Fanout to 15 F devices
SCR-latchup-resistant CMOS process and circuit design

Inputs are TTL-voltage compatible
Contain six flip-flops with single-rail outputs
Buffered inputs
Speed of bipolar F, AS, and S, with significantly reduced power consumption
Balanced propagation delays
±24mA output drive current
- Fanout to 15 F devices
SCR-latchup-resistant CMOS process and circuit design

The ’ACT174 devices are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input and are designed for 4.5V to 5.5V VCC operation.

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	類型	標題		日期
*	Data sheet	CDx4ACT174 Hex D-Type Flip-Flops with Clear datasheet (Rev. A)	PDF \| HTML	2024年 4月 18日
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	2022年 12月 15日
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		2021年 7月 26日
	Selection guide	Logic Guide (Rev. AB)		2017年 6月 12日
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015年 12月 2日
	User guide	LOGIC Pocket Data Book (Rev. B)		2007年 1月 16日
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004年 7月 8日
	Application note	Selecting the Right Level Translation Solution (Rev. A)		2004年 6月 22日
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		2002年 8月 29日
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		1997年 6月 1日
	Application note	Designing With Logic (Rev. C)		1997年 6月 1日
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc		1996年 4月 1日