CD74ACT273
- Buffered inputs
- Typical propagation delay
- 6.5ns at VCC = 5V, T A = 25°C, CL = 50pF
- SCR-latchup-resistant CMOS process and circuit design
- Speed of Bipolar FAST™/AS/S with significantly reduced power consumption
- Balanced propagation delays
- AC types feature 1.5v to 5.5v operation and balanced noise immunity at 30% of the supply
- ±24mA output drive current
- Fanout to 15 FAST™ ICs
- Drives 50Ω transmission lines
The ’AC273 and ’ACT273 devices are octal D-type flip-flops with reset that utilize advanced CMOS logic technology. Information at the D input is transferred to the Q output on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CDx4AC273, CDx4ACT273 Octal D Flip-Flop with Reset datasheet (Rev. C) | PDF | HTML | 2024/5/8 | ||
| 應用說明 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022/12/15 |
設計與開發
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開發板
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SSOP (DB) | 20 | Ultra Librarian |
| SOIC (DW) | 20 | Ultra Librarian |
| TSSOP (PW) | 20 | Ultra Librarian |
| PDIP (N) | 20 | Ultra Librarian |