CD74FCT843A

Name: CD74FCT843A
Brand: TI
SKU: CD74FCT843A
Price: 3.479 USD

現行

具有 3 態輸出的 BiCMOS FCT 介面邏輯 9 位元非反相透明鎖存器

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產品規格表

document-pdfAcrobat BiCMOS 9-Bit Bus-Interface D-Type Latch With 3-State Outputs datasheet (英文)

CD74FCT843A

現行

產品規格表

立即訂購

產品詳細資料

Number of channels

9

Technology family

FCT

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

70

IOL (max) (mA)

48

IOH (max) (mA)

-15

Supply current (max) (µA)

80

Features

Flow-through pinout, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

Number of channels

9

Technology family

FCT

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

70

IOL (max) (mA)

48

IOH (max) (mA)

-15

Supply current (max) (µA)

80

Features

Flow-through pinout, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

BiCMOS Technology With Low Quiescent Power
Buffered Inputs
Noninverted Outputs
Input/Output Isolation From V_CC
Controlled Output Edge Rates
48-mA Output Sink Current
Output Voltage Swing Limited to 3.7 V
SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
Packaged in Plastic Small-Outline Package

BiCMOS Technology With Low Quiescent Power
Buffered Inputs
Noninverted Outputs
Input/Output Isolation From V_CC
Controlled Output Edge Rates
48-mA Output Sink Current
Output Voltage Swing Limited to 3.7 V
SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
Packaged in Plastic Small-Outline Package

The CD74FCT843A is a 9-bit, bus-interface, D-type latch with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below V_CC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes V_CC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA.

The CD74FCT843A outputs are transparent to the inputs when the latch-enable (LE) input is high. The latches are transparent D-type latches. When LE goes low, the data is latched. The output-enable (OE\) input controls the 3-state outputs. When OE\ is high, the outputs are in the high-impedance state. The latch operation is independent of the state of the output enable. This device, having preset (PRE\) and clear (CLR\), are ideal for parity-bus interfacing. When PRE\ is low, the outputs are high if OE\ is low. PRE\ overrides CLR\. When CLR\ is low, the outputs are low if OE\ is low. When CLR\ is high, data can be entered into the latch. The device provides noninverted outputs.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

The CD74FCT843A is characterized for operation from 0°C to 70°C.

The CD74FCT843A is a 9-bit, bus-interface, D-type latch with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below V_CC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes V_CC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA.

The CD74FCT843A outputs are transparent to the inputs when the latch-enable (LE) input is high. The latches are transparent D-type latches. When LE goes low, the data is latched. The output-enable (OE\) input controls the 3-state outputs. When OE\ is high, the outputs are in the high-impedance state. The latch operation is independent of the state of the output enable. This device, having preset (PRE\) and clear (CLR\), are ideal for parity-bus interfacing. When PRE\ is low, the outputs are high if OE\ is low. PRE\ overrides CLR\. When CLR\ is low, the outputs are low if OE\ is low. When CLR\ is high, data can be entered into the latch. The device provides noninverted outputs.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

The CD74FCT843A is characterized for operation from 0°C to 70°C.

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