CD74HC4046A
- Operating Frequency Range
- Up to 18MHz (Typ) at VCC = 5V
- Minimum Center Frequency of 12MHz at VCC = 4.5V
- Choice of Three Phase Comparators
- EXCLUSIVE-OR
- Edge-Triggered JK Flip-Flop
- Edge-Triggered RS Flip-Flop
- Excellent VCO Frequency Linearity
- VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
- Minimal Frequency Drift
- Operating Power Supply Voltage Range
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
- Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
- Wide Operating Temperature Range . . . -55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
- Applications
- FM Modulation and Demodulation
- Frequency Synthesis and Multiplication
- Frequency Discrimination
- Tone Decoding
- Data Synchronization and Conditioning
- Voltage-to-Frequency Conversion
- Motor-Speed Control
The ’HC4046A and ’HCT4046A are high-speed silicon-gate CMOS devices that are pin compatible with the CD4046B of the "4000B" series. They are specified in compliance with JEDEC standard number 7.
The ’HC4046A and ’HCT4046A are phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator.
The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A datasheet (Rev. J) | 2003/11/21 | |||
| 應用說明 | Implementation of FSK Modulation and Demodulation using CD74HC4046A | 2013/11/25 | ||||
| 應用說明 | Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency | 2008/3/31 | ||||
| 應用說明 | CMOS Phase-Locked-Loop Applications (Rev. B) | 2002/9/19 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| PDIP (N) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
| SOIC (D) | 16 | Ultra Librarian |
| SOP (NS) | 16 | Ultra Librarian |