CD74HC4094-Q1
- AEC-Q100 qualified for automotive applications:
- Device temperature grade 1: -40°C to +125°C
- Device HBM ESD classification level 2
- Device CDM ESD classification level C4B
- Buffered inputs
- Separate serial outputs synchronous to both positive and negative clock edges for cascading
- Balanced propagation delay and transition times
- Significant power reduction compared to LSTTL logic ICs
The CD74HC4094-Q1 contains 8-stage serial shift registers with a storage latch associated with each stage for strobing data from the serial input to parallel buffered tri-state outputs. The parallel outputs can connect directly to common bus lines. Data shifts on positive clock transitions. When the Strobe input is high, the data in each shift register stage transfers to the storage register. Data in the storage register appears at the outputs when the Output-Enable signal is high.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CD74HC4094-Q1 Automotive High-Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State datasheet | PDF | HTML | 2026/8/3 |
設計與開發
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開發板
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 16 | Ultra Librarian |