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微控制器 (MCU) 與處理器
微處理器和 DSP
音訊與雷達 DSP SoC

DRA787

現行

適用於音訊放大器且具有 2 個 750 MHz C66x DSP 和 2 個雙 Arm Cortex-M4 和 EVE 的 SoC 處理器

立即訂購
產品規格表
使用指南

DRA787

現行
產品規格表 立即訂購

產品詳細資料

Coprocessors 2 Dual Arm Cortex-M4 Display type 1 LCD OUT, 1 SD-DAC Protocols Ethernet PCIe 2 PCIe Gen2 Hardware accelerators 1 Audio Tracking Logic Features Multimedia Operating system Android, Linux, RTOS TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution LP873220-Q1, LP87332D-Q1, TPS65917-Q1, TPS65919-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled No
Coprocessors 2 Dual Arm Cortex-M4 Display type 1 LCD OUT, 1 SD-DAC Protocols Ethernet PCIe 2 PCIe Gen2 Hardware accelerators 1 Audio Tracking Logic Features Multimedia Operating system Android, Linux, RTOS TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution LP873220-Q1, LP87332D-Q1, TPS65917-Q1, TPS65919-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCBGA (ABF) 367 225 mm² (15 mm × 15 mm)
  • Architecture designed for infotainment applications
  • Up to 2 C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512kB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • Memory Interface (EMIF) module
    • Supports DDR3/DDR3L up to DDR-1066
    • Supports DDR2 up to DDR-800
    • Up to 2GB supported
  • Dual Arm® Cortex®-M4 (IPU)
  • Vision accelerationPac
    • Embedded Vision Engine (EVE)
  • Display subsystem
    • Display controller with DMA engine
    • CVIDEO / SD-DAC TV analog composite output
  • On-chip temperature sensor that is capable of generating temperature alerts
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 3-port (2 external) Gigabit Ethernet (GMAC) switch
  • Controller Area Network (DCAN) module
    • CAN 2.0B protocol
  • Modular Controller Area Network (MCAN) module
    • CAN 2.0B protocol
  • Eight 32-bit general-purpose timers
  • Three configurable UART modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI interface
  • Two Inter-Integrated Circuit (I2C™) ports
  • Three Multichannel Audio Serial Port (McASP) modules
  • Secure Digital Input Output Interface (SDIO)
  • Up to 126 General-Purpose I/O (GPIO) pins
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • Automotive AEC-Q100 qualified
  • 15 × 15 mm, 0.65-mm pitch, 367-pin PBGA (ABF)
  • Five instances of Real-Time Interrupt (RTI) modules that can be used as watch dog timers
  • 8-channel 10-bit ADC
  • PWMSS
  • Video and image processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Video input and video output
    • GPIOs when not used for video
  • Video Input Port (VIP) module
    • Support for up to 4 multiplexed input ports
  • Architecture designed for infotainment applications
  • Up to 2 C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512kB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • Memory Interface (EMIF) module
    • Supports DDR3/DDR3L up to DDR-1066
    • Supports DDR2 up to DDR-800
    • Up to 2GB supported
  • Dual Arm® Cortex®-M4 (IPU)
  • Vision accelerationPac
    • Embedded Vision Engine (EVE)
  • Display subsystem
    • Display controller with DMA engine
    • CVIDEO / SD-DAC TV analog composite output
  • On-chip temperature sensor that is capable of generating temperature alerts
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 3-port (2 external) Gigabit Ethernet (GMAC) switch
  • Controller Area Network (DCAN) module
    • CAN 2.0B protocol
  • Modular Controller Area Network (MCAN) module
    • CAN 2.0B protocol
  • Eight 32-bit general-purpose timers
  • Three configurable UART modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI interface
  • Two Inter-Integrated Circuit (I2C™) ports
  • Three Multichannel Audio Serial Port (McASP) modules
  • Secure Digital Input Output Interface (SDIO)
  • Up to 126 General-Purpose I/O (GPIO) pins
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • Automotive AEC-Q100 qualified
  • 15 × 15 mm, 0.65-mm pitch, 367-pin PBGA (ABF)
  • Five instances of Real-Time Interrupt (RTI) modules that can be used as watch dog timers
  • 8-channel 10-bit ADC
  • PWMSS
  • Video and image processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Video input and video output
    • GPIOs when not used for video
  • Video Input Port (VIP) module
    • Support for up to 4 multiplexed input ports

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8 mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8 mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 DRA78x Infotainment Applications Processor datasheet (Rev. H) PDF | HTML 2020/2/4
* 使用指南 DRA78x Technical Reference Manual (Rev. D) 2019/7/30
* 勘誤表 DRA78x Silicon Errata (Rev. B) 2019/10/1
應用說明 Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 2021/5/5
應用說明 IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 2020/8/24
應用說明 AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 2020/1/6
應用說明 Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 2019/6/11
應用說明 Achieving Early CAN Response on DRA7xx Devices 2018/11/28
應用說明 DRA74x_75x/DRA72x Performance (Rev. A) 2018/10/31
應用說明 Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices 2018/9/14
應用說明 The Implementation of YUV422 Output for SRV 2018/8/2
應用說明 MMC DLL Tuning (Rev. B) 2018/7/31
應用說明 Integrating AUTOSAR on TI SoC: Fundamentals 2018/6/18
應用說明 ECC/EDC on TDAxx (Rev. B) 2018/6/13
應用說明 Tools and Techniques to Root Case Failures in Video Capture Subsystem 2018/6/12
應用說明 Sharing VPE Between VISIONSDK and PSDKLA 2018/5/4
應用說明 Android Boot Optimization on DRA7xx Devices (Rev. A) 2018/2/13
應用說明 Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) 2017/11/30
應用說明 Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) 2017/11/27
應用說明 Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 2017/11/7
應用說明 A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 2017/11/3
應用說明 Optimization of GPU-Based Surround View on TI’s TDA2x SoC 2017/9/12
應用說明 Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices 2017/8/14
應用說明 Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices 2017/7/12
應用說明 Linux Boot Time Optimizations on DRA7xx Devices 2017/3/31
應用說明 Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) 2017/2/17
應用說明 Early Splash Screen on DRA7x Devices 2017/1/31
應用說明 Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 2016/12/15
應用說明 Gstreamer Migration Guidelines 2016/4/26
應用說明 Flashing Binaries to DRA7xx Factory Boards Using DFU 2016/4/14
應用說明 Tools and Techniques for Audio Debugging 2016/4/13
應用說明 Debugging Tools and Techniques With IPC3.x 2016/3/30
應用說明 Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) 2016/1/15
白皮書 Informational ADAS as Software Upgrade to Today’s Infotainment Systems 2014/10/14
應用說明 Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 2014/8/13
白皮書 Today’s high-end infotainment soon becoming mainstream 2014/6/2

設計與開發

電源供應解決方案

為 DRA787 尋找可用的電源供應解決方案。TI 提供適用於 TI 與非 TI 之系統單晶片 (SoC)、處理器、微控制器、感測器或現場可編程邏輯閘陣列 (FPGA) 的電源供應解決方案。

檢視解決方案
開發板

DRA78XEVM — DRA78x 評估模組

The Jacinto™ DRA78x evaluation module (EVM) is an evaluation platform designed to speed up development efforts and reduce time-to-market for Radio Signal Processor (RSP) applications. The EVM is based on the Jacinto DRA78x SoC, which incorporates a heterogeneous, scalable architecture (...)

使用指南: PDF
從：SVTRONICS INC
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偵錯探測器

LB-3P-TRACE32-DSP — 適用於數位訊號處理器 (DSP) 的 Lauterbach TRACE32 偵錯和追蹤系統

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

從：Lauterbach GmbH
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軟體開發套件 (SDK)

PROCESSOR-SDK-ANDROID-AUTOMOTIVE-DRA7X

處理器 SDK Linux Automotive

處理器 SDK Linux Automotive 是 TI 的 Jacinto™ DRAx 資訊娛樂系統 SoC 系列的基礎軟體開發平台。軟體架構可讓使用者開發功能豐富的車載資訊娛樂系統解決方案，例如新一代汽車適用之可重新配置的數位儀表總成、整合式駕駛艙、車內資訊娛樂系統、無線數據通訊、後座娛樂等。SDK 是以通用處理器 SDK 平台為基礎。

焦點
  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) 工具鏈
  • Yocto Project™ OE Core 相容檔案系統
(...)
支援產品和硬體
軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X — PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X

處理器 SDK Linux Automotive

處理器 SDK Linux Automotive 是 TI 的 Jacinto™ DRAx 資訊娛樂系統 SoC 系列的基礎軟體開發平台。軟體架構可讓使用者開發功能豐富的車載資訊娛樂系統解決方案，例如新一代汽車適用之可重新配置的數位儀表總成、整合式駕駛艙、車內資訊娛樂系統、無線數據通訊、後座娛樂等。SDK 是以通用處理器 SDK 平台為基礎。

焦點
  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) 工具鏈
  • Yocto Project™ OE Core 相容檔案系統
(...)
支援產品和硬體
軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-AUTOMOTIVE-DRA7X

處理器 SDK Linux Automotive

處理器 SDK Linux Automotive 是 TI 的 Jacinto™ DRAx 資訊娛樂系統 SoC 系列的基礎軟體開發平台。軟體架構可讓使用者開發功能豐富的車載資訊娛樂系統解決方案，例如新一代汽車適用之可重新配置的數位儀表總成、整合式駕駛艙、車內資訊娛樂系統、無線數據通訊、後座娛樂等。SDK 是以通用處理器 SDK 平台為基礎。

焦點
  • 長期穩定 (LTS) Mainline Linux 核心支援
  • U-Boot 開機載入程式支援
  • Linaro GNU 編譯器系列 (GCC) 工具鏈
  • Yocto Project™ OE Core 相容檔案系統
(...)
支援產品和硬體
IDE、配置、編譯器或偵錯程式

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

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作業系統 (OS)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
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支援軟體

VCTR-3P-MICROSAR — 適用於微控制器和高性能電腦 (HPC) 的 Vector MICROSAR AUTOSAR 軟體

MICROSAR 與 DaVinci 產品系列透過適用於微控制器與 HPC 的精密嵌入式軟體和強大開發工具，簡化 ECU 開發。有了先進的基礎架構軟體，您即可為 ECU 建立最佳基礎，並利用相關工具簡化所有相關開發作業。MICROSAR 嵌入式軟體是根據 AUTOSAR 經典和適應性等相關標準所開發。軟體也適合符合最高 ASIL D 之 ISO 26262 標準的安全相關應用。此外，智慧網路安全功能可保護控制單元免受未經授權的存取和竄改。Vector 涵蓋所有汽車與其他工業應用的使用案例。對於配備高性能電腦的軟體定義車輛 (SDV)，其可提供現代車輛作業系統，以做為開放式模組化軟體生態系統。

從：Vector Informatik GmbH
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模擬型號

DRA78x BSDL Model

SPRM713.ZIP (9 KB) - BSDL 模型
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模擬型號

DRA78x IBIS Model

SPRM703.ZIP (10940 KB) - IBIS 模型
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模擬型號

DRA78x Thermal Model

SPRM704.ZIP (1 KB) - 熱模型
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計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
支援產品和硬體
封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (ABF) 367 Ultra Librarian
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