封裝資訊
| 封裝 | 針腳 VSON (REU) | 8 |
| 操作溫度範圍 (°C) -40 to 125 |
| 包裝數量 | 運送業者 3,000 | LARGE T&R |
ISO6521 的特色
- Dual channel, CMOS output functional isolators
- 50Mbps data rate
- Robust SiO2 isolation barrier with ±150kV/µs typical CMTI
- Functional Isolation (8-REU):
- 450VRMS, 637VDC working voltage
- 2000VRMS, 2828VDC transient voltage (60s)
- Functional Isolation (8-D):
- 450VRMS, 637VDC working voltage
- 2000VRMS, 2828VDC transient voltage (60s)
- Available in a compact 8-REU package with >2.2mm creepage
- Wide supply range: 1.71V to 1.89V and 2.25V to 5.5V
- 1.71V to 5.5V level translation
- Default output High (ISO652x) and Low (ISO652xF) Options
- Wide temperature range: –40°C to 125°C
- 1.8mA per channel typical at 1Mbps at 3.3V
- Low propagation delay: 11ns typical at 3.3V
- Robust electromagnetic compatibility (EMC)
- System-Level ESD, EFT, and surge immunity
- Ultra-low emissions
- Leadless-DFN (8-REU) package and Narrow-SOIC (8-D) package options
ISO6521 的說明
The ISO652x devices are high-performance, dual-channel functional isolators designed for cost sensitive, space constrained applications that require isolation for non-safety applications. The isolation barrier supports a working voltage of 450VRMS / 637VDC and transient over voltages of 2000VRMS / 2828VDC.
The devices provide high electromagnetic immunity and low emissions at low power consumption, while isolating CMOS or LVCMOS digital I/Os. Each isolation channel has a logic input and output buffer separated by TI’s double capacitive silicon dioxide (SiO2) insulation barrier. ISO6520 has two isolation channels with both channels in the same direction. ISO6521 has two isolation channels with one channel in each direction. In the event of input power or signal loss, the default output is high for devices without suffix F and low for devices with suffix F. See Device Functional Modes section for further details.
These devices help prevent noise currents on data buses, such as UART, SPI, RS-485, RS-232, and CAN from damaging sensitive circuitry. Through chip design and layout techniques, the electromagnetic compatibility of the devices have been significantly enhanced to ease system-level ESD and emissions compliance.