SN10KHT5574

Name: SN10KHT5574
Brand: TI
SKU: SN10KHT5574
Price: 10.567 USD

現行

具有 D 型邊緣觸發正反器和 3 態輸出的八路 ECL 至 TTL 轉換器

立即訂購

產品規格表

document-pdfAcrobat Octal ECL-to-TTL Translator w/D-Type Edge-Triggered FF & 3-State Outputs datasheet (英文)

SN10KHT5574

現行

產品規格表

立即訂購

產品詳細資料

Bits (#)

8

Data rate (max) (Mbps)

2

Topology

Open drain, Push-Pull

Vin (min) (V)

4.7

Vin (max) (V)

5.5

Applications

GTL

Features

Partial power down (Ioff), Single supply

Technology family

TTL

Supply current (max) (mA)

110

Rating

Catalog

Operating temperature range (°C)

0 to 70

Bits (#)

8

Data rate (max) (Mbps)

2

Topology

Open drain, Push-Pull

Vin (min) (V)

4.7

Vin (max) (V)

5.5

Applications

GTL

Features

Partial power down (Ioff), Single supply

Technology family

TTL

Supply current (max) (mA)

110

Rating

Catalog

Operating temperature range (°C)

0 to 70

SOIC (DW)

24

159.65 mm² 15.5 x 10.3

10KH Compatible
ECL Clock and TTL Control Inputs
Flow-Through Architecture Optimizes PCB Layout
Center Pin V_CC, V_EE, and GND Configurations Minimize High-Speed Switching Noise
Package Options Include "Small Outline" Packages and Standard Plastic DIPs

10KH Compatible
ECL Clock and TTL Control Inputs
Flow-Through Architecture Optimizes PCB Layout
Center Pin V_CC, V_EE, and GND Configurations Minimize High-Speed Switching Noise
Package Options Include "Small Outline" Packages and Standard Plastic DIPs

This octal ECL-to-TTL translator is designed to provide efficient translation between a 10KH ECL signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The eight flip-flops of the SN10KHT5574 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels that were set up at the D inputs.

A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

The output-enable input OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are off.

The SN10KHT5574 is characterized for operation from 0°C to 75°C.

This octal ECL-to-TTL translator is designed to provide efficient translation between a 10KH ECL signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The eight flip-flops of the SN10KHT5574 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels that were set up at the D inputs.

A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

The output-enable input OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are off.

The SN10KHT5574 is characterized for operation from 0°C to 75°C.

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