SN54ABT377
- State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
- High-Drive Outputs (-32-mA IOH, 64-mA IOL)
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package
EPIC-IIB is a trademark of Texas Instruments Incorporated.
These 8-bit positive-edge-triggered D-type flip-flops with a clock (CLK) input are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators.
Data (D) input information that meets the setup time requirements
is transferred to the Q outputs on the positive-going edge of the
clock pulse if the common clock-enable (
) input is low. Clock triggering
occurs at a particular voltage level and is not directly related to
the transition time of the positive-going pulse. When the buffered
clock (CLK) input is at either the high or low level, the D-input
signal has no effect at the output. The circuits are designed to
prevent false clocking by transitions at .
The SN54ABT377 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT377A is characterized for operation from -40°C to 85°C.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | Octal Edge-Triggered D-Type Flip-Flops With Clock Enable datasheet (Rev. E) | 1997年 1月 1日 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點