SN54AHC138
- Operating range 2V to 5.5V VCC
- Designed specifically for high-speed memory decoders and data-transmission systems
- Incorporate three enable inputs to simplify cascading and/or data reception
- Latch-up performance exceeds 250mA per JESD 17
- ESD protection exceeds JESD 22:
- 2000V Human-Body Model (A114-A)
- 1000V Charged-Device Model (C101)
The SNx4AHC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SNx4AHC138 3-Line to 8-Line Decoders/Demultiplexers datasheet (Rev. N) | PDF | HTML | 2024/7/24 | ||
| * | SMD | SN54AHC138 SMD 5962-98516 | 2016/6/21 |