產品詳細資料

Function Counter Bits (#) 4 Technology family ALS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
Function Counter Bits (#) 4 Technology family ALS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 20 167.464 mm² 24.2 x 6.92 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • 3-State Q Outputs Drive Bus Lines Directly
  • Counter Operation Independent of 3-State Output
  • Fully Synchronous Clear, Count, and Load
  • Asynchronous Clear Is Also Provided
  • Fully Cascadable
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

  • 3-State Q Outputs Drive Bus Lines Directly
  • Counter Operation Independent of 3-State Output
  • Fully Synchronous Clear, Count, and Load
  • Asynchronous Clear Is Also Provided
  • Fully Cascadable
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

The SN74ALS568A decade counter and ´ALS569A binary counters are programmable, count up or down, and offer both synchronous and asynchronous clearing. All synchronous functions are executed on the positive-going edge of the clock (CLK) input.

The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). Asynchronous (direct) clearing overrides all other functions of the device, while synchronous clearing overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by holding load () low during a positive-going clock transition. The counting function is enabled only when enable P (ENP\) and enable T (ENT\) are low and ACLR\, SCLR\, and are high. The up/down (U/D\) input controls the direction of the count. These counters count up when U/D\ is high and count down when U/D\ is low.

A high level at the output-enable () input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of . ENT\ is fed forward to enable the ripple-carry output (RCO\) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum (9 or 15) when counting up. The clocked carry output (CCO\) produces a low-level pulse for a duration equal to that of the low level of the clock when is low and the counter is enabled (both ENP\ and ENT\ are low); otherwise, CCO\ is high. CCO\ does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connecting or CCO\ of the first counter to ENT\ of the next counter. However, for very high-speed counting, should be used for cascading since CCO\ does not become active until the clock returns to the low level.

The SN54ALS569A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS568A and SN74ALS569A are characterized for operation from 0°C to 70°C.

 

 

The SN74ALS568A decade counter and ´ALS569A binary counters are programmable, count up or down, and offer both synchronous and asynchronous clearing. All synchronous functions are executed on the positive-going edge of the clock (CLK) input.

The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). Asynchronous (direct) clearing overrides all other functions of the device, while synchronous clearing overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by holding load () low during a positive-going clock transition. The counting function is enabled only when enable P (ENP\) and enable T (ENT\) are low and ACLR\, SCLR\, and are high. The up/down (U/D\) input controls the direction of the count. These counters count up when U/D\ is high and count down when U/D\ is low.

A high level at the output-enable () input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of . ENT\ is fed forward to enable the ripple-carry output (RCO\) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum (9 or 15) when counting up. The clocked carry output (CCO\) produces a low-level pulse for a duration equal to that of the low level of the clock when is low and the counter is enabled (both ENP\ and ENT\ are low); otherwise, CCO\ is high. CCO\ does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connecting or CCO\ of the first counter to ENT\ of the next counter. However, for very high-speed counting, should be used for cascading since CCO\ does not become active until the clock returns to the low level.

The SN54ALS569A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS568A and SN74ALS569A are characterized for operation from 0°C to 70°C.

 

 

下載 觀看有字幕稿的影片 影片

您可能會感興趣的類似產品

open-in-new 比較替代產品
功能相似於所比較的產品
最新 SN74LV393B-EP 現行 增強型產品雙路四位元二進位計數器 Voltage range (2V to 5.5V), average drive strength (12mA), average propagation delay (9ns)

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 12
類型 標題 日期
* Data sheet Synchronous 4-Bit Up/Down Decade And Binary Counters With 3-State Outputs datasheet (Rev. A) 1995年 1月 1日
* SMD SN54ALS569A SMD 83025022A 2016年 6月 21日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Advanced Schottky (ALS and AS) Logic Families 1995年 8月 1日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

封裝 針腳 CAD 符號、佔位空間與 3D 模型
CDIP (J) 20 Ultra Librarian
LCCC (FK) 20 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片