SN54HC573A

現行

具有 3 態輸出的八路 D 型透明鎖存器

產品詳細資料

Number of channels 8 Technology family HC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 28 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Supply current (max) (µA) 160 Features Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 8 Technology family HC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 28 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Supply current (max) (µA) 160 Features Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
LCCC (FK) 20 79.0321 mm² (— mm × — mm) CFP (W) 20 90.5828 mm² (— mm × — mm) CDIP (J) 20 167.464 mm² (— mm × — mm)
  • Wide Operating Voltage Range from 2 V to 6 V
  • High-Current 3-State Outputs Drive Bus Lines Directly up to 15 LSTTL Loads
  • Low Power Consumption: 80-µA Maximum ICC
  • Typical tpd = 21 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current: 1 µA (Maximum)
  • Bus-Structured Pinout
  • Wide Operating Voltage Range from 2 V to 6 V
  • High-Current 3-State Outputs Drive Bus Lines Directly up to 15 LSTTL Loads
  • Low Power Consumption: 80-µA Maximum ICC
  • Typical tpd = 21 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current: 1 µA (Maximum)
  • Bus-Structured Pinout

The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.

The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SNx4HC573A Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. G) PDF | HTML 2022/4/20
* SMD SN54HC573A SMD 85128012A 2016/6/21

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