SN54LS137
- Combines Decoder and 3-Bit Address Latch
- Incorporates 2 Enable Inputs to Simplify Cascading
- Low Power Dissipation … 65 mW Typ
The 'LS137 is a three-line to eight-line decoder/demultiplexer with latches on the three address inputs. When the latch-enable input (GL\) is low, the 'LS137 acts as a decoder/demultiplexer. When GL\ goes from low to high, the address present at the select inputs (A, B, and C) is stored in the latches. Further address changes are ignored as long as GL\ remains high. The output enable controls, G1 and G\2, control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are high unless G1 is high and G\2 is low. The 'LS137 is ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 3-Line To 8-Line Decoders/Demultiplexers With Address Latches datasheet | 1988/3/1 |