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SN54LVC00A-SP

現行

QML-V, 4-ch, 2-input, 2V to 3.6V NAND gates

立即訂購
產品規格表

SN54LVC00A-SP

現行
立即訂購

產品詳細資料

Technology family LVC Number of channels 4 Inputs per channel 2 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Space Operating temperature range (°C) -55 to 125
Technology family LVC Number of channels 4 Inputs per channel 2 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Space Operating temperature range (°C) -55 to 125
CFP (W) 14 58.023 mm² (— mm × — mm)
  • ESD protection exceeds JESD 22
    • 2000V Human-Body Model
    • 1000V Charged-Device Model
  • SN74LVC00A operates from 1.65V to 3.6V
  • SN54LVC00A operates from 2V to 3.6V
  • SNx4LVC00A specified from –40°C to +85°C and –40°C to +125°C
  • SN54LVC00A specified from –55°C to +125°C
  • Inputs accept voltages to 5.5V
  • Max tpd of 4.3ns at 3.3V
  • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250 mA per JESD 17
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
  • ESD protection exceeds JESD 22
    • 2000V Human-Body Model
    • 1000V Charged-Device Model
  • SN74LVC00A operates from 1.65V to 3.6V
  • SN54LVC00A operates from 2V to 3.6V
  • SNx4LVC00A specified from –40°C to +85°C and –40°C to +125°C
  • SN54LVC00A specified from –55°C to +125°C
  • Inputs accept voltages to 5.5V
  • Max tpd of 4.3ns at 3.3V
  • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250 mA per JESD 17
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

The SN54LVC00A quadruple 2-input positive-NAND gate is designed for 2.7V to 3.6V VCC operation, and the SN74LVC00A quadruple 2-input positive-NAND gate is designed for 1.65V to 3.6V VCC operation.

The SNx4LVC00A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment.

The SN54LVC00A quadruple 2-input positive-NAND gate is designed for 2.7V to 3.6V VCC operation, and the SN74LVC00A quadruple 2-input positive-NAND gate is designed for 1.65V to 3.6V VCC operation.

The SNx4LVC00A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SNx4LVC00A Quadruple 2-Input Positive-NAND Gates datasheet (Rev. U) PDF | HTML 2024/7/29
* SMD SN54LVC00A-SP SMD 5962-97533 2016/7/8
選擇指南 TI Space Products (Rev. L) 2026/3/27
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 2025/6/17
應用說明 Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 2025/6/10
更多文件說明 TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 2025/2/20
應用說明 Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022/10/19

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