SN54LVC138A
- Operate From 1.65 V to 3.6 V
- Inputs Accept Voltages to 5.5 V
- Max tpd of 5.8 ns at 3.3 V
- Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
- Latch-Up Performance Exceeds 250 mA Per JESD 17
The SN74LVC138A devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
技術文件
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74LVC138A 3-Line to 8-Line Decoders Demultiplexers datasheet (Rev. W) | PDF | HTML | 2016/11/11 | ||
| * | SMD | SN54LVC138A SMD 5962-97526 | 2016/6/21 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| CFP (W) | 16 | Ultra Librarian |
| CDIP (J) | 16 | Ultra Librarian |
| LCCC (FK) | 20 | Ultra Librarian |