首頁 邏輯和電壓轉換 正反器、鎖存器和暫存器 D 型鎖存器
首頁
邏輯和電壓轉換
正反器、鎖存器和暫存器
D 型鎖存器

SN54LVC373A

現行

具有 3 態輸出的八路透明 D 型鎖存器

立即訂購
產品規格表

SN54LVC373A

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 8 Technology family LVC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 8 Technology family LVC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
LCCC (FK) 20 79.0321 mm² (— mm × — mm) CFP (W) 20 90.5828 mm² (— mm × — mm) CDIP (J) 20 167.464 mm² (— mm × — mm)
  • Operate From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 6.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation
    on All Ports
    (5-V Input/Output Voltage With 3.3-V VCC)
  • Ioff Supports Live-Insertion, Partial-Power-Down Mode,
    and Back-Drive Protection
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • On Products Compliant to MIL-PRF-38535, All
    Parameters Are Tested Unless Otherwise Noted.
    On All Other Products, Production Processing
    Does Not Necessarily Include Testing of All
    Parameters.
  • Operate From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 6.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation
    on All Ports
    (5-V Input/Output Voltage With 3.3-V VCC)
  • Ioff Supports Live-Insertion, Partial-Power-Down Mode,
    and Back-Drive Protection
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • On Products Compliant to MIL-PRF-38535, All
    Parameters Are Tested Unless Otherwise Noted.
    On All Other Products, Production Processing
    Does Not Necessarily Include Testing of All
    Parameters.

The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

For all available packages, see the orderable addendum at the end of the data sheet.

The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

For all available packages, see the orderable addendum at the end of the data sheet.
filter 尋找其它 D 型鎖存器
下載 觀看有字幕稿的影片 影片

技術文件

找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 3
重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SNx4LVC373A Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. T) PDF | HTML 2013/11/21
* SMD SN54LVC373A SMD 5962-97573 2016/6/21
應用說明 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

封裝 針腳 CAD 符號、佔位空間與 3D 模型
LCCC (FK) 20 Ultra Librarian
CFP (W) 20 Ultra Librarian
CDIP (J) 20 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片