首頁 邏輯和電壓轉換 正反器、鎖存器和暫存器 D 型正反器
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邏輯和電壓轉換
正反器、鎖存器和暫存器
D 型正反器

SN54LVC74A

現行

具清除和預設功能的雙正緣觸發 D 型正反器

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產品規格表

SN54LVC74A

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 2 Technology family LVC Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family LVC Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
CFP (W) 14 58.023 mm² (— mm × — mm) CDIP (J) 14 130.4652 mm² (— mm × — mm) LCCC (FK) 20 79.0321 mm² (— mm × — mm)
  • Operate from 1.65V to 3.6V
  • Inputs accept voltages to 5.5V
  • Maximum tpd of 5.2ns at 3.3V
  • Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250mA per JESD 17
  • ESD protection exceeds JESD 22
    • 2000V human-body model (A114-A)
    • 1000V charged-device model (C101)
  • Operate from 1.65V to 3.6V
  • Inputs accept voltages to 5.5V
  • Maximum tpd of 5.2ns at 3.3V
  • Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250mA per JESD 17
  • ESD protection exceeds JESD 22
    • 2000V human-body model (A114-A)
    • 1000V charged-device model (C101)

The SNx4LVC74A devices integrate two positive-edge triggered D-type flip-flops in one convenient device.

The SN54LVC74A is designed for 2.7V to 3.6V VCC operation, and the SN74LVC74A is designed for 1.65V to 3.6V VCC operation.

The SNx4LVC74A devices integrate two positive-edge triggered D-type flip-flops in one convenient device.

The SN54LVC74A is designed for 2.7V to 3.6V VCC operation, and the SN74LVC74A is designed for 1.65V to 3.6V VCC operation.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset datasheet (Rev. W) PDF | HTML 2024/12/19
* SMD SN54LVC74A SMD 5962-97616 2016/6/21
應用說明 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
CFP (W) 14 Ultra Librarian
CDIP (J) 14 Ultra Librarian
LCCC (FK) 20 Ultra Librarian
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