首頁 介面 LVDS、M-LVDS 和 PECL IC
首頁
介面
LVDS、M-LVDS 和 PECL IC

SN65LVDS3486

現行

四路 LVDS 接收器

立即訂購
產品規格表

SN65LVDS3486

現行
產品規格表 立即訂購

產品詳細資料

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (MBits) 100 Input signal LVDS Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (MBits) 100 Input signal LVDS Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Meet or Exceed the Requirements of ANSI
    TIA/EIA-644 Standard
  • Operate With a Single 3.3-V Supply
  • Designed for Signaling Rates of up to
    150 Mbps
  • Differential Input Thresholds ±100 mV Max
  • Typical Propagation Delay Time of 2.1 ns
  • Power Dissipation 60 mW Typical Per
    Receiver at Maximum Data Rate
  • Bus-Terminal ESD Protection Exceeds 8 kV
  • Low-Voltage TTL (LVTTL) Logic Output
    Levels
  • Pin Compatible With AM26LS32, MC3486,
    and µA9637
  • Open-Circuit Fail-Safe
  • Cold Sparing for Space and High-Reliability
    Applications Requiring Redundancy
  • Meet or Exceed the Requirements of ANSI
    TIA/EIA-644 Standard
  • Operate With a Single 3.3-V Supply
  • Designed for Signaling Rates of up to
    150 Mbps
  • Differential Input Thresholds ±100 mV Max
  • Typical Propagation Delay Time of 2.1 ns
  • Power Dissipation 60 mW Typical Per
    Receiver at Maximum Data Rate
  • Bus-Terminal ESD Protection Exceeds 8 kV
  • Low-Voltage TTL (LVTTL) Logic Output
    Levels
  • Pin Compatible With AM26LS32, MC3486,
    and µA9637
  • Open-Circuit Fail-Safe
  • Cold Sparing for Space and High-Reliability
    Applications Requiring Redundancy

The SN55LVDS32, SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 devices are differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.

The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 devices are characterized for operation from –40°C to 85°C. The SN55LVDS32 device is characterized for operation from –55°C to 125°C.

The SN55LVDS32, SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 devices are differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.

The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 devices are characterized for operation from –40°C to 85°C. The SN55LVDS32 device is characterized for operation from –55°C to 125°C.
open-in-new 尋找其它 LVDS、M-LVDS 和 PECL IC
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 5
類型 標題 日期
* Data sheet SNx5LVDS32, SN65LVDS3486, SN65LVDS9637 High-Speed Differential Line Receivers datasheet (Rev. R) 2014年 8月 6日
Application brief LVDS to Improve EMC in Motor Drives 2018年 9月 27日
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 2018年 8月 3日
Application brief How to Terminate LVDS Connections with DC and AC Coupling 2018年 5月 16日
Application note An Overview of LVDS Technology 1998年 10月 5日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

SN65LVDS3486 IBIS Model (Rev. A)

SLLC013A.ZIP (4 KB) - IBIS Model
下載
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
檢視選項
封裝 引腳 下載
SOIC (D) 16 檢視選項
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 資格摘要
  • 進行中可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片