SN65LVDS93A-Q1
- AEC-Q100 Qualified with:
- Temperature Grade 3: –40°C to 85°C
- HBM ESD Classification 3
- CDM ESD Classification C6
- LVDS Display Series Interfaces Directly to LCD
Display Panels With Integrated LVDS - Package: 14-mm × 6.1-mm TSSOP
- 1.8-V Up to 3.3-V Tolerant Data Inputs to Connect
Directly to Low-Power, Low-Voltage Application
and Graphic Processors - Transfer Rate up to 135 Mpps (Mega Pixel Per
Second); Pixel Clock Frequency Range 10 MHz to
135 MHz - Suited for Display Resolutions Ranging From
HVGA up to HD With Low EMI - Operates From a Single 3.3-V Supply and 170
mW (Typical) at 75 MHz - 28 Data Channels Plus Clock in Low-Voltage TTL
to 4 Data Channels Plus Clock Out Low-Voltage
Differential - Consumes Less Than 1 mW When Disabled
- Selectable Rising or Falling Clock Edge Triggered
Inputs - Support Spread Spectrum Clocking (SSC)
- Compatible with all OMAP™ 2x, OMAP™ 3x, and
DaVinci™ Application Processors
The SN65LVDS93A-Q1 FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS94 and LCD panels with integrated LVDS receiver.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN65LVDS93A-Q1 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.
The SN65LVDS93A-Q1 is characterized for operation over ambient air temperatures of –40°C to 85°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN65LVDS93A-Q1 FlatLink™ Transmitter datasheet (Rev. B) | PDF | HTML | 2015/4/16 | ||
| 應用說明 | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018/11/9 | ||||
| 應用說明 | AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (Rev. A) | 2018/8/3 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
LVDS83BTSSOPEVM — LVDS83BT 10-135 MHz 28 位元 LVDS 發送器/串聯器評估模組
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。