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SN74ABT125Q-Q1

現行

具有 TTL 相容 CMOS 輸入和 3 態輸出的車用 4 通道、4.5-V 至 5.5-V 緩衝器

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產品規格表

SN74ABT125Q-Q1

現行
產品規格表 立即訂購

產品詳細資料

Technology family ABT Number of channels 4 IOL (max) (mA) 32 Supply current (max) (µA) 30000 IOH (max) (mA) -16 Input type TTL-Compatible CMOS Output type 3-State Features Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Automotive Operating temperature range (°C) -40 to 125
Technology family ABT Number of channels 4 IOL (max) (mA) 32 Supply current (max) (µA) 30000 IOH (max) (mA) -16 Input type TTL-Compatible CMOS Output type 3-State Features Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Automotive Operating temperature range (°C) -40 to 125
SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm)
  • Qualified for Automotive Applications
  • Typical VOLP (Output Ground Bounce)
       <1 V at VCC = 5 V, TA = 25°C
  • High-Drive Outputs
       (–16-mA IOH, 32-mA IOL)
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Qualified for Automotive Applications
  • Typical VOLP (Output Ground Bounce)
       <1 V at VCC = 5 V, TA = 25°C
  • High-Drive Outputs
       (–16-mA IOH, 32-mA IOL)
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

The SN74ABT125Q-Q1 quadruple bus buffer gate features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74ABT125Q-Q1 quadruple bus buffer gate features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 Quadruple Bus Buffer Gate With 3-State Outputs datasheet (Rev. B) 2008/1/18
更多文件說明 Automotive Logic Devices Brochure 2014/8/27

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