SN74ABT16825

現行

具有 TTL 相容 CMOS 輸入和 3 態輸出的 18 通道、4.5-V 至 5.5-V 緩衝器

立即訂購

產品規格表

document-pdfAcrobat 18-Bit Buffers/Drivers 18-Bit Buffers/Drivers With 3-State Outputs datasheet (Rev. D) (英文)

SN74ABT16825

現行

產品規格表

立即訂購

產品詳細資料

Technology family

ABT

Number of channels

18

IOL (max) (mA)

64

Supply current (max) (µA)

32000

IOH (max) (mA)

-32

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

ABT

Number of channels

18

IOL (max) (mA)

64

Supply current (max) (µA)

32000

IOH (max) (mA)

-32

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SSOP (DL)

56

190.647 mm² (18.42 mm × 10.35 mm)

Members of Texas Instruments' Widebus^TM Family
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD 17
Typical V_OLP (Output Ground Bounce)
<1 V at V_CC = 5 V, T_A = 25°C
High-Impedance State During Power Up and Power Down
Distributed V_CC and GND Pins Minimize High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)

Widebus is a trademark of Texas Instruments.

Members of Texas Instruments' Widebus^TM Family
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD 17
Typical V_OLP (Output Ground Bounce)
<1 V at V_CC = 5 V, T_A = 25°C
High-Impedance State During Power Up and Power Down
Distributed V_CC and GND Pins Minimize High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)

Widebus is a trademark of Texas Instruments.

The 'ABT16825 devices are 18-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices can be used as two 9-bit buffers or one 18-bit buffer. They provide true data.

The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1\ or OE2\) input is high, all nine affected outputs are in the high-impedance state.

When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The 'ABT16825 devices are 18-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices can be used as two 9-bit buffers or one 18-bit buffer. They provide true data.

The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1\ or OE2\) input is high, all nine affected outputs are in the high-impedance state.

When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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