SN74AC534

現行

具有 3 態輸出的八路邊緣觸發 D 型正反器

SN74AC534

現行

產品詳細資料

Number of channels 8 Technology family AC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 8 Technology family AC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 85 Rating Catalog
PDIP (N) 20 228.702 mm² (24.33 mm × 9.4 mm) TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm) SSOP (DB) 20 56.16 mm² (7.2 mm × 7.8 mm) SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) SOP (NS) 20 98.28 mm² (12.6 mm × 7.8 mm)
  • Operation of 2V to 6V VCC
  • Inputs accept voltages to 6V
  • Max tpd of 11ns at 5V
  • 3-state inverting outputs drive bus lines directly
  • Full parallel access for loading
  • Operation of 2V to 6V VCC
  • Inputs accept voltages to 6V
  • Max tpd of 11ns at 5V
  • 3-state inverting outputs drive bus lines directly
  • Full parallel access for loading

These octal edge-triggered D-type flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These octal edge-triggered D-type flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74AC534 Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs datasheet (Rev. F) PDF | HTML 2024/2/29
應用說明 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15

設計與開發

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開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
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PDIP (N) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian
SOP (NS) 20 Ultra Librarian

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