SN74AHCT139

Name: SN74AHCT139
Brand: TI
SKU: SN74AHCT139
Price: 0.085 USD

現行

二路 2 線路至 4 線路解碼器/解多工器

立即訂購

產品規格表

document-pdfAcrobat SN54AHCT139, SN74AHCT139 datasheet (Rev. M) (英文)

SN74AHCT139

現行

產品規格表

立即訂購

產品詳細資料

Technology family

AHCT

Number of channels

2

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Supply current (max) (µA)

20

Technology family

AHCT

Number of channels

2

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Supply current (max) (µA)

20

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

SSOP (DB)

16

48.36 mm² 6.2 x 7.8

TSSOP (PW)

16

32 mm² 5 x 6.4

TVSOP (DGV)

16

23.04 mm² 3.6 x 6.4

Inputs Are TTL-Voltage Compatible
Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Inputs Are TTL-Voltage Compatible
Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

The ’AHCT139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 4.5-V to 5.5-V V_CC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The active-low enable (G)\ input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

The ’AHCT139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 4.5-V to 5.5-V V_CC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The active-low enable (G)\ input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

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SN74HCT139

現行

二路 2 線路至 4 線路解碼器/解多工器 Voltage range (4.5V to 5.5V), average drive strength (4mA), average propagation delay (22ns)

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	類型	標題	日期
*	Data sheet	SN54AHCT139, SN74AHCT139 datasheet (Rev. M)	2003年 3月 7日
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	2021年 7月 26日
	Selection guide	Little Logic Guide 2018 (Rev. G)	2018年 7月 6日
	Selection guide	Logic Guide (Rev. AB)	2017年 6月 12日
	Application note	How to Select Little Logic (Rev. A)	2016年 7月 26日
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	2015年 12月 2日
	User guide	LOGIC Pocket Data Book (Rev. B)	2007年 1月 16日
	Product overview	Design Summary for WCSP Little Logic (Rev. B)	2004年 11月 4日
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	2004年 7月 8日
	Application note	Selecting the Right Level Translation Solution (Rev. A)	2004年 6月 22日
	Application note	Advanced High-Speed CMOS (AHC) Logic Family (Rev. C)	2002年 12月 2日
	Application note	Texas Instruments Little Logic Application Report	2002年 11月 1日
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	2002年 8月 29日
	Design guide	AHC/AHCT Designer's Guide February 2000 (Rev. D)	2000年 2月 24日
	Product overview	Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C)	1998年 4月 1日
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	1997年 12月 1日
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	1997年 8月 1日
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	1997年 6月 1日
	Application note	Live Insertion	1996年 10月 1日

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14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML

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模擬型號

HSPICE Model of SN74AHCT139

SCLJ005.ZIP (53 KB) - HSpice Model

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模擬型號

SN74AHCT139 IBIS Model

SCLM093.ZIP (14 KB) - IBIS Model

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封裝	針腳	CAD 符號、佔位空間與 3D 模型
PDIP (N)	16	Ultra Librarian
SOIC (D)	16	Ultra Librarian
SSOP (DB)	16	Ultra Librarian
TSSOP (PW)	16	Ultra Librarian
TVSOP (DGV)	16	Ultra Librarian

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SN74AHCT139

二路 2 線路至 4 線路解碼器/解多工器

SN74AHCT139

產品詳細資料

您可能會感興趣的類似產品

功能相同，但引腳輸出與所比較的裝置不同

技術文件

設計與開發

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

HSPICE Model of SN74AHCT139

SN74AHCT139 IBIS Model

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