SN74ALS843
- 3-State Buffer-Type Outputs Drive Bus Lines Directly
- Bus-Structured Pinout
- Provides Extra Bus-Driving Latches Necessary for Wider Address/Data Paths or Buses With Parity
- Buffered Control Inputs to Reduce
dc Loading Effects - Power-Up High-Impedance State
- Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs
This 9-bit bus-interface D-type latch features 3-state outputs
designed specifically for driving
highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The nine latches are transparent D-type latches with noninverting data (D) inputs.
A buffered output-enable () input places the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
does not affect the internal operation of the latches. Previously stored data can be retained or new data can be entered while the outputs are off.
The SN74ALS843 is characterized for operation from 0°C to 70°C.
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技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | 9-Bit Bus-Interface D-Type Latch With 3-State Outputs datasheet (Rev. A) | 1995年 1月 1日 | |
Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022年 12月 15日 | |
Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||
Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997年 8月 1日 | ||
Application note | Designing With Logic (Rev. C) | 1997年 6月 1日 | ||
Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996年 10月 1日 | ||
Application note | Live Insertion | 1996年 10月 1日 | ||
Application note | Advanced Schottky (ALS and AS) Logic Families | 1995年 8月 1日 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
封裝 | 引腳 | 下載 |
---|---|---|
SOIC (DW) | 24 | 檢視選項 |
訂購與品質
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- 產品標記
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- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點