產品詳細資料

Technology family ALVC Bits (#) 16 High input voltage (min) (V) 1.7 High input voltage (max) (V) 5.5 Vout (min) (V) 2.3 Vout (max) (V) 5.5 Data rate (max) (Mbps) 300 IOH (max) (mA) -24 IOL (max) (mA) 24 Supply current (max) (µA) 40 Features Output enable Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family ALVC Bits (#) 16 High input voltage (min) (V) 1.7 High input voltage (max) (V) 5.5 Vout (min) (V) 2.3 Vout (max) (V) 5.5 Data rate (max) (Mbps) 300 IOH (max) (mA) -24 IOL (max) (mA) 24 Supply current (max) (µA) 40 Features Output enable Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • Member of the Texas Instruments Widebus™ Family
  • Maximum tpd of 5.8 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • APPLICATIONS
    • Electronic Points of Sale
    • Printers and Other Peripherals
    • Motor Drives
    • Wireless and Telecom Infrastructures
    • Wearable Health and Fitness Devices

All other trademarks are the property of their respective owners

  • Member of the Texas Instruments Widebus™ Family
  • Maximum tpd of 5.8 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • APPLICATIONS
    • Electronic Points of Sale
    • Printers and Other Peripherals
    • Motor Drives
    • Wireless and Telecom Infrastructures
    • Wearable Health and Fitness Devices

All other trademarks are the property of their respective owners

This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails. B port has VCCB, which is set to operate at 3.3 V and 5 V. A port has VCCA, which is set to operate at 2.5 V and 3.3 V. This allows for translation from a 2.5-V to a 3.3-V environment, and vice versa, or from a 3.3-V to a 5-V environment, and vice versa.

The SN74ALVC164245 is designed for asynchronous communication between data buses. The control circuitry (1DIR, 2DIR, 1OE, and 2OE) is powered by VCCA.

To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails. B port has VCCB, which is set to operate at 3.3 V and 5 V. A port has VCCA, which is set to operate at 2.5 V and 3.3 V. This allows for translation from a 2.5-V to a 3.3-V environment, and vice versa, or from a 3.3-V to a 5-V environment, and vice versa.

The SN74ALVC164245 is designed for asynchronous communication between data buses. The control circuitry (1DIR, 2DIR, 1OE, and 2OE) is powered by VCCA.

To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

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類型 標題 日期
* Data sheet SN74ALVC164245 16-Bit 2.5-V to 3.3-V or 3.3-V to 5-V Level-Shifting Transceiver With 3-State Outputs datasheet (Rev. Q) PDF | HTML 2016年 9月 27日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in CMOS Output Buffers PDF | HTML 2024年 5月 14日
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 2024年 4月 30日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 2002年 8月 1日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999年 9月 8日
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 1998年 8月 3日
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 1998年 5月 13日
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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模擬型號

SN74ALVC164245 IBIS Model (Rev. C)

SCEM026C.ZIP (58 KB) - IBIS Model
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian

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