SN74ALVCF162835

現行

具有 3 態輸出的 3.3V CMOS 18 位元通用匯流排驅動器

立即訂購

產品規格表

document-pdfAcrobat SN74ALVCF162835 datasheet (Rev. A) (英文)

SN74ALVCF162835

現行

產品規格表

立即訂購

產品詳細資料

Number of channels

18

IOL (max) (mA)

18

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns)

Technology family

ALVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Number of channels

18

IOL (max) (mA)

18

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns)

Technology family

ALVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

TVSOP (DGV)

56

72.32 mm² (11.3 mm × 6.4 mm)

TSSOP (DGG)

56

113.4 mm² (14 mm × 8.1 mm)

Member of the Texas Instruments Widebus™ Family
Ideal for Use in PC133 Register DIMM
Typical Output Skew . . . <250 ps
V_CC = 3.3 V ± 0.3 V . . . Normal Range
V_CC = 2.7 V to 3.6 V . . . Extended Range
V_CC = 2.5 V ± 0.2 V
Rail-to-Rail Output Swing for Increased Noise Margin
Balanced Output Drivers . . . ±18 mA
Low Switching Noise
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

Member of the Texas Instruments Widebus™ Family
Ideal for Use in PC133 Register DIMM
Typical Output Skew . . . <250 ps
V_CC = 3.3 V ± 0.3 V . . . Normal Range
V_CC = 2.7 V to 3.6 V . . . Extended Range
V_CC = 2.5 V ± 0.2 V
Rail-to-Rail Output Swing for Increased Noise Margin
Balanced Output Drivers . . . ±18 mA
Low Switching Noise
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

This 18-bit universal bus driver is designed for 2.3-V to 3.6-V V_CC operation.

Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

The SN74ALVCF162835 has series damping resistors in the device output structure that reduce switching noise in 128-MB and 256-MB SDRAM modules. Designed with a drive capability of ±18 mA, this device is a midway drive between the SN74ALVC162835 (±12 mA) and SN74ALVC16835 (±24 mA).

The SN74ALVCF162835 is a faster version of the SN74ALVC162835. It is suitable for PC133 applications and, particularly, SDRAM modules clocked at 133 MHz.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 18-bit universal bus driver is designed for 2.3-V to 3.6-V V_CC operation.

Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

The SN74ALVCF162835 has series damping resistors in the device output structure that reduce switching noise in 128-MB and 256-MB SDRAM modules. Designed with a drive capability of ±18 mA, this device is a midway drive between the SN74ALVC162835 (±12 mA) and SN74ALVC16835 (±24 mA).

The SN74ALVCF162835 is a faster version of the SN74ALVC162835. It is suitable for PC133 applications and, particularly, SDRAM modules clocked at 133 MHz.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

filter

尋找其它通用收發器

下載觀看有字幕稿的影片影片