SN74AUC16240

現行

具有 3 態輸出的 16 通道、0.8-V 至 2.7-V 高速逆變器

立即訂購

產品規格表

document-pdfAcrobat SN74AUC16240 datasheet (Rev. E) (英文)

SN74AUC16240

現行

產品規格表

立即訂購

產品詳細資料

Technology family

AUC

Number of channels

16

IOL (max) (mA)

9

IOH (max) (mA)

-9

Supply current (max) (µA)

20

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AUC

Number of channels

16

IOL (max) (mA)

9

IOH (max) (mA)

-9

Supply current (max) (µA)

20

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

TSSOP (DGG)

48

101.25 mm² (12.5 mm × 8.1 mm)

TVSOP (DGV)

48

62.08 mm² (9.7 mm × 6.4 mm)

Member of the Texas Instruments Widebus™ Family
Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial-Power-Down Mode Operation
Sub 1-V Operable
Max t_pd of 2 ns at 1.8 V
Low Power Consumption, 20-uA Max I_CC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

Member of the Texas Instruments Widebus™ Family
Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial-Power-Down Mode Operation
Sub 1-V Operable
Max t_pd of 2 ns at 1.8 V
Low Power Consumption, 20-uA Max I_CC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

This 16-bit buffer/driver is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC16240 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides inverting outputs and symmetrical active-low output-enable (OE)\ inputs.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This 16-bit buffer/driver is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC16240 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides inverting outputs and symmetrical active-low output-enable (OE)\ inputs.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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