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正反器、鎖存器和暫存器
D 型正反器

SN74AUCH16374

現行

具有 3 態輸出的 16 位元邊緣觸發 D 型正反器

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產品規格表

SN74AUCH16374

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 16 Technology family AUC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 250 IOL (max) (mA) 9 IOH (max) (mA) -9 Supply current (max) (µA) 20 Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 16 Technology family AUC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 250 IOL (max) (mA) 9 IOH (max) (mA) -9 Supply current (max) (µA) 20 Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Operating temperature range (°C) -40 to 85 Rating Catalog
TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm) TVSOP (DGV) 48 62.08 mm² (9.7 mm × 6.4 mm)
  • Member of the Texas Instruments Widebus Family
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant
    to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Sub-1-V Operable
  • Max tpd of 2.8 ns at 1.8 V
  • Low Power Consumption, 20 µA Max ICC
  • ±8-mA Output Drive at 1.8 V
  • Bus Hold on Data Inputs Eliminates the Need for External
    Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.
  • Member of the Texas Instruments Widebus Family
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant
    to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Sub-1-V Operable
  • Max tpd of 2.8 ns at 1.8 V
  • Low Power Consumption, 20 µA Max ICC
  • ±8-mA Output Drive at 1.8 V
  • Bus Hold on Data Inputs Eliminates the Need for External
    Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

This 16-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This 16-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74AUCH16374 datasheet (Rev. E) 2012/8/25
應用說明 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15

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模擬型號

SN74AUCH16374 IBIS Model (Rev. A)

SCEM351 (436 KB) - IBIS 模型
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TSSOP (DGG) 48 Ultra Librarian
TVSOP (DGV) 48 Ultra Librarian
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