產品詳細資料

Protocols DDR2 Configuration 4:1 Number of channels 11 Bandwidth (MHz) 400 Ron (typ) (mΩ) 10000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 1.9 Supply current (typ) (µA) 700 ESD HBM (typ) (kV) 2.5 Operating temperature range (°C) 0 to 85 ESD CDM (kV) 0.75 Input/output continuous current (max) (mA) 100 COFF (typ) (pF) 2.5 CON (typ) (pF) 4.6 OFF-state leakage current (max) (µA) 10 Propagation delay time (µs) 0.000297 Ron (max) (mΩ) 17000 RON flatness (typ) (Ω) 1.5 Turnoff time (disable) (max) (ns) 2.1 Turnon time (enable) (max) (ns) 2.1 VIH (min) (V) 1.1 VIL (max) (V) 0.66 Rating Catalog
Protocols DDR2 Configuration 4:1 Number of channels 11 Bandwidth (MHz) 400 Ron (typ) (mΩ) 10000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 1.9 Supply current (typ) (µA) 700 ESD HBM (typ) (kV) 2.5 Operating temperature range (°C) 0 to 85 ESD CDM (kV) 0.75 Input/output continuous current (max) (mA) 100 COFF (typ) (pF) 2.5 CON (typ) (pF) 4.6 OFF-state leakage current (max) (µA) 10 Propagation delay time (µs) 0.000297 Ron (max) (mΩ) 17000 RON flatness (typ) (Ω) 1.5 Turnoff time (disable) (max) (ns) 2.1 Turnon time (enable) (max) (ns) 2.1 VIH (min) (V) 1.1 VIL (max) (V) 0.66 Rating Catalog
NFBGA (ZST) 72 49 mm² (7 mm × 7 mm)
  • Supports SSTL_18 signaling levels
  • Suitable for DDR-II applications
  • D-port outputs are precharged by bias voltage (VBIAS)
  • Internal termination for control inputs
  • High bandwidth (400 MHz minimum)
  • Low and flat ON-state resistance (ron) characteristics, (ron = 17 Ω maximum)
  • Internal 400-Ω pulldown resistors
  • Low differential and rising or falling edge skew
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • Supports SSTL_18 signaling levels
  • Suitable for DDR-II applications
  • D-port outputs are precharged by bias voltage (VBIAS)
  • Internal termination for control inputs
  • High bandwidth (400 MHz minimum)
  • Low and flat ON-state resistance (ron) characteristics, (ron = 17 Ω maximum)
  • Internal 400-Ω pulldown resistors
  • Low differential and rising or falling edge skew
  • Latch-up performance exceeds 100 mA per JESD 78, Class II

The SN74CBTU4411 device is a high-bandwidth, SSTL_18 compatible FET multiplexer/demultiplexer with low ON-state resistance (ron). The device uses an internal charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ron. The low and flat ron allows for minimal propagation delay and supports rail-to-rail signaling on data input/output (I/O) ports. The device also features very low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Matched ron and I/O capacitance among channels results in extremely low differential and rising or falling edge skew. This allows the device to show optimal performance in DDR-II applications.

The SN74CBTU4411 device is a high-bandwidth, SSTL_18 compatible FET multiplexer/demultiplexer with low ON-state resistance (ron). The device uses an internal charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ron. The low and flat ron allows for minimal propagation delay and supports rail-to-rail signaling on data input/output (I/O) ports. The device also features very low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Matched ron and I/O capacitance among channels results in extremely low differential and rising or falling edge skew. This allows the device to show optimal performance in DDR-II applications.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74CBTU4411 11-Bit 1-of-4 Multiplexer or Demultiplexer 1.8-V DDR-II Switch With Charge Pump and Precharged Outputs datasheet (Rev. C) PDF | HTML 2021/9/13
Application brief 1.8-V Logic for Multiplexers and Signal Switches (Rev. C) PDF | HTML 2022/7/26

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HSPICE Model for SN74CBTU4411

SCDJ034.ZIP (101 KB) - HSpice 模型
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SN74CBTU4411 IBIS Model

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
NFBGA (ZST) 72 Ultra Librarian

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