產品詳細資料

Bits (#) 12 Data rate (max) (Mbps) 200 Topology Open drain, Push-Pull Direction control (typ) Fixed-direction Vin (min) (V) 3 Vin (max) (V) 3.6 Applications GTL Features Overvoltage tolerant inputs Technology family GTL Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 12 Data rate (max) (Mbps) 200 Topology Open drain, Push-Pull Direction control (typ) Fixed-direction Vin (min) (V) 3 Vin (max) (V) 3.6 Applications GTL Features Overvoltage tolerant inputs Technology family GTL Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (PW) 28 62.08 mm² (9.7 mm × 6.4 mm)
  • Operates as a GTL-/GTL/GTL+ to LVTTL or LVTTL to GTL-/GTL/GTL+ Translator
  • Series Termination on TTL Output of 30
  • Latch-Up Testing Done to JEDEC Standard JESD 78
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Xeon is a trademark of Intel Corporation.

  • Operates as a GTL-/GTL/GTL+ to LVTTL or LVTTL to GTL-/GTL/GTL+ Translator
  • Series Termination on TTL Output of 30
  • Latch-Up Testing Done to JEDEC Standard JESD 78
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Xeon is a trademark of Intel Corporation.

The SN74GTL2107 is a 12-bit translator that interfaces between the 3.3-V LVTTL chip set I/O and the Xeon™ processor GTL-/GTL/GTL+ I/O. The device is designed for platform health management in dual-processor applications.

The SN74GTL2107 is a 12-bit translator that interfaces between the 3.3-V LVTTL chip set I/O and the Xeon™ processor GTL-/GTL/GTL+ I/O. The device is designed for platform health management in dual-processor applications.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74GTL2107 datasheet 2006/7/1
應用說明 Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024/7/12
應用說明 Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024/7/3

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模擬型號

HSPICE Model for SN74GTL2107

SCLM102.ZIP (109 KB) - HSpice 模型
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模擬型號

SN74GTL2107 IBIS Model

SLLM075.ZIP (32 KB) - IBIS 模型
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (PW) 28 Ultra Librarian

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