產品詳細資料

Technology family LS Bits (#) 1 Rating Catalog Operating temperature range (°C) 0 to 70
Technology family LS Bits (#) 1 Rating Catalog Operating temperature range (°C) 0 to 70
PDIP (N) 16 181.42 mm² 19.3 x 9.4
  • Count Divider Chain
  • Digitally Programmable from 22 to 2n
    (n = 31 for SN74LS292 , n = 15 for SN74LS294)
  • Useable Frequency Range from DC to 30 MHz
  • Easily Expandable
  • Count Divider Chain
  • Digitally Programmable from 22 to 2n
    (n = 31 for SN74LS292 , n = 15 for SN74LS294)
  • Useable Frequency Range from DC to 30 MHz
  • Easily Expandable

The SN74LS29x devices are programmable frequency dividers and digital timers contain 31 flip-flops plus 30 gates (in SN74LS292) or 15 flip-flops plus 29 gates (in SN74LS294) on a single chip. The count modulo is under digital control of the inputs provided.

Both types feature an active-low CLR clear input to initialize the state of all flip-flops. To facilitate the incoming inspection, test points are provided (TP1, TP2, and TP3 on the SN74LS292, and TP on the SN74LS294). These test points are not intended to drive system loads. Both types feature two clock inputs; either one may be used for clock gating.

A brief look at the digital timing capabilities of the SN74LS292 shows that with a 1-MHz input frequency, programming for 210 gives a period of 1.024 ms, 220 gives a period of 1.05 sec, 226 gives a period of 1.12 min, and 231 gives a period of 35.79 min.

These devices are easily cascadable, giving limitless possibilities to achievable timing delays.

The SN74LS29x devices are programmable frequency dividers and digital timers contain 31 flip-flops plus 30 gates (in SN74LS292) or 15 flip-flops plus 29 gates (in SN74LS294) on a single chip. The count modulo is under digital control of the inputs provided.

Both types feature an active-low CLR clear input to initialize the state of all flip-flops. To facilitate the incoming inspection, test points are provided (TP1, TP2, and TP3 on the SN74LS292, and TP on the SN74LS294). These test points are not intended to drive system loads. Both types feature two clock inputs; either one may be used for clock gating.

A brief look at the digital timing capabilities of the SN74LS292 shows that with a 1-MHz input frequency, programming for 210 gives a period of 1.024 ms, 220 gives a period of 1.05 sec, 226 gives a period of 1.12 min, and 231 gives a period of 35.79 min.

These devices are easily cascadable, giving limitless possibilities to achievable timing delays.

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類型 標題 日期
* Data sheet SN74LS29x Programmable Frequency Dividers and Digital Timers datasheet (Rev. A) PDF | HTML 2016年 1月 7日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Designing with the SN54/74LS123 (Rev. A) 1997年 3月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日

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