產品詳細資料

Technology family LV1T Number of channels 1 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -8 IOL (max) (mA) 8 Supply current (max) (µA) 10 Features Over-voltage tolerant inputs, Single supply, Voltage translation Input type TTL-Compatible CMOS Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 125
Technology family LV1T Number of channels 1 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -8 IOL (max) (mA) 8 Supply current (max) (µA) 10 Features Over-voltage tolerant inputs, Single supply, Voltage translation Input type TTL-Compatible CMOS Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1
  • Single-supply voltage translator at 5.0-V, 3.3-V, 2.5-V, and 1.8-V V CC
  • Operating range of 1.8 V to 5.5 V
  • Up translation:
    • 1.2 V (1) to 1.8 V at 1.8-V V CC
    • 1.5 V (1) to 2.5 V at 2.5-V V CC
    • 1.8 V (1) to 3.3 V at 3.3-V V CC
    • 3.3 V to 5.0 V at 5.0-V V CC
  • Down translation:
    • 3.3 V to 1.8 V at 1.8-V V CC
    • 3.3 V to 2.5 V at 2.5-V V CC
    • 5.0 V to 3.3 V at 3.3-V V CC
  • Logic output is referenced to V CC
  • Output drive:
    • 8 mA output drive at 5 V
    • 7 mA output drive at 3.3 V
    • 3 mA output drive at 1.8 V
  • Characterized up to 50 MHz at 3.3-V V CC
  • 5V Tolerance on input pins
  • –40°C to 125°C operating temperature range
  • Pb-free packages available: SC-70 (DCK)
    • 2 × 2.1 × 0.65 mm (height 1.1 mm)
  • Latch-up performance exceeds 250 mA per JESD 17
  • Supports standard logic pinouts
  • CMOS output B compatible with AUP1G and LVC1G families (1)

(1)Refer to the V IH/V IL and output drive for lower V CC condition.

  • Single-supply voltage translator at 5.0-V, 3.3-V, 2.5-V, and 1.8-V V CC
  • Operating range of 1.8 V to 5.5 V
  • Up translation:
    • 1.2 V (1) to 1.8 V at 1.8-V V CC
    • 1.5 V (1) to 2.5 V at 2.5-V V CC
    • 1.8 V (1) to 3.3 V at 3.3-V V CC
    • 3.3 V to 5.0 V at 5.0-V V CC
  • Down translation:
    • 3.3 V to 1.8 V at 1.8-V V CC
    • 3.3 V to 2.5 V at 2.5-V V CC
    • 5.0 V to 3.3 V at 3.3-V V CC
  • Logic output is referenced to V CC
  • Output drive:
    • 8 mA output drive at 5 V
    • 7 mA output drive at 3.3 V
    • 3 mA output drive at 1.8 V
  • Characterized up to 50 MHz at 3.3-V V CC
  • 5V Tolerance on input pins
  • –40°C to 125°C operating temperature range
  • Pb-free packages available: SC-70 (DCK)
    • 2 × 2.1 × 0.65 mm (height 1.1 mm)
  • Latch-up performance exceeds 250 mA per JESD 17
  • Supports standard logic pinouts
  • CMOS output B compatible with AUP1G and LVC1G families (1)

(1)Refer to the V IH/V IL and output drive for lower V CC condition.

The SN74LV1T02 is a single 2-input NOR gate with reduced input thresholds to support voltage translation applications.

The SN74LV1T02 is a single 2-input NOR gate with reduced input thresholds to support voltage translation applications.

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類型 標題 日期
* Data sheet SN74LV1T02Single Power Supply 2-Input Positive NOR GateCMOS Logic Level Shifter datasheet (Rev. C) PDF | HTML 2023年 10月 30日
Application note LV1T Family of single supply translators (Rev. B) PDF | HTML 2022年 12月 16日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
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模擬型號

SN74LV1T02 Behavioral SPICE Model

SCLM185.ZIP (7 KB) - PSpice Model
模擬型號

SN74LV1T02 IBIS Model (Rev. A)

SCLM106A.ZIP (44 KB) - IBIS Model
封裝 引腳 下載
SOT-23 (DBV) 5 檢視選項
SOT-SC70 (DCK) 5 檢視選項

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