SN74LVC112A

現行

具有清除和預設功能的二路負緣觸發 J-K 正反器

立即訂購

產品規格表

document-pdfAcrobat SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop with Clear and Preset datasheet (Rev. O) (英文) PDF | HTML

SN74LVC112A

現行

立即訂購

產品詳細資料

Number of channels

Technology family

LVC

Input type

TTL/CMOS

Output type

Push-Pull

Clock frequency (MHz)

150

Supply current (max) (µA)

IOL (max) (mA)

IOH (max) (mA)

-24

Features

Balanced outputs, Clear, Negative edge triggered, Over-voltage tolerant inputs, Preset, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Number of channels

Technology family

LVC

Input type

TTL/CMOS

Output type

Push-Pull

Clock frequency (MHz)

150

Supply current (max) (µA)

IOL (max) (mA)

IOH (max) (mA)

-24

Features

Balanced outputs, Clear, Negative edge triggered, Over-voltage tolerant inputs, Preset, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Catalog

TSSOP (PW)

32 mm² (5 mm × 6.4 mm)

SOP (NS)

79.56 mm² (10.2 mm × 7.8 mm)

SOIC (D)

59.4 mm² (9.9 mm × 6 mm)

SSOP (DB)

48.36 mm² (6.2 mm × 7.8 mm)

TVSOP (DGV)

23.04 mm² (3.6 mm × 6.4 mm)

Operates from 1.65V to 3.6V
Inputs accept voltages to 5.5V
Max tpd of 4.8ns at 3.3V
Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, TA = 25°C
Latch-up performance exceeds 250mA per JESD 17

Operates from 1.65V to 3.6V
Inputs accept voltages to 5.5V
Max tpd of 4.8ns at 3.3V
Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, TA = 25°C
Latch-up performance exceeds 250mA per JESD 17

This dual negative-edge-triggered J-K flip-flop is designed for 1.65V to 3.6V VCC operation.

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重要文件	類型	標題	格式選項	下載最新的英文版本		日期
*	資料表	SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop with Clear and Preset datasheet (Rev. O)	PDF \| HTML		2025/7/6
	應用說明	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML		2022/12/15