SN74LVC16373A

現行

具有 3 態輸出的 16 位元透明 D 型鎖存器

立即訂購

產品規格表

document-pdfAcrobat SN74LVC16373A 16-Bit Transparent D-Type Latch With 3-State Outputs datasheet (Rev. B) (英文) PDF | HTML

SN74LVC16373A

現行

產品規格表

立即訂購

產品詳細資料

Number of channels

Technology family

LVC

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

100

IOL (max) (mA)

IOH (max) (mA)

-24

Supply current (max) (µA)

Features

Balanced outputs, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Number of channels

Technology family

LVC

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

100

IOL (max) (mA)

IOH (max) (mA)

-24

Supply current (max) (µA)

Features

Balanced outputs, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Catalog

SSOP (DL)

164.358 mm² (15.88 mm × 10.35 mm)

TVSOP (DGV)

62.08 mm² (9.7 mm × 6.4 mm)

TSSOP (DGG)

101.25 mm² (12.5 mm × 8.1 mm)

Member of the Texas Instruments
Widebus™ Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.2 ns at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live-Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Supports Mixed-Mode Signal Operation (5-V Input
and Outputand Output Voltages With 3.3-V V_CC)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

Member of the Texas Instruments
Widebus™ Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.2 ns at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live-Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Supports Mixed-Mode Signal Operation (5-V Input
and Outputand Output Voltages With 3.3-V V_CC)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

The SN74LVC16373A device is a 16-bit transparent D-type latch which is designed for 1.65-V to 3.6-V V_CC operation.

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重要文件	類型	標題	格式選項	下載最新的英文版本		日期
*	資料表	SN74LVC16373A 16-Bit Transparent D-Type Latch With 3-State Outputs datasheet (Rev. B)	PDF \| HTML			2014/2/5
	應用說明	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML			2022/12/15