SN74LVC1G86-Q1

現行

汽車類單 2 輸入 1.65-V 至 5.5-V XOR (exclusive OR) 閘

產品詳細資料

Technology family LVC Number of channels 1 Inputs per channel 2 IOL (max) (mA) 32 Input type Standard CMOS IOH (max) (mA) -32 Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Automotive Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 1 Inputs per channel 2 IOL (max) (mA) 32 Input type Standard CMOS IOH (max) (mA) -32 Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Automotive Operating temperature range (°C) -40 to 125
SOT-SC70 (DCK) 5 4.2 mm² (2 mm × 2.1 mm)
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • ±4000-V Human-Body Model (HBM) ESD Classification Level 3A
    • ±1000-V Charged-Device Model (CDM) ESD Classification Level C5
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Low Power Consumption, 15-µA Maximum ICC
  • Maximum tpd of 6 ns at 3.3 V and 50-pF load
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • ±4000-V Human-Body Model (HBM) ESD Classification Level 3A
    • ±1000-V Charged-Device Model (CDM) ESD Classification Level C5
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Low Power Consumption, 15-µA Maximum ICC
  • Maximum tpd of 6 ns at 3.3 V and 50-pF load
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

The SN74LVC1G86-Q1 is an automotive qualified device that performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.

If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum tpd of 6 ns at 3.3 V and 50-pF capacitive load. The max output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

The SN74LVC1G86-Q1 is an automotive qualified device that performs the Boolean function Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.

If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device has low power consumption with maximum tpd of 6 ns at 3.3 V and 50-pF capacitive load. The max output drive is ±32-mA at 4.5 V and ±24-mA at 3.3 V.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back flow through the device when it is powered down.

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* 資料表 SN74LVC1G86-Q1 Single 2-Input Exclusive-OR Gate datasheet PDF | HTML 2016/10/4

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5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

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SN74LVC1G86 Behavioral SPICE Model

SCEM627.ZIP (7 KB) - PSpice 模型
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SN74LVC1G86 IBIS Model (Rev. A)

SCEM186 (243 KB) - IBIS 模型
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SOT-SC70 (DCK) 5 Ultra Librarian

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