TB5T1

現行

5-V 雙路全雙工 PECL 收發器

產品詳細資料

Function Transceiver Protocols PECL Number of transmitters 2 Number of receivers 2 Supply voltage (V) 5 Signaling rate (MBits) 100 Input signal PECL, TTL Output signal PECL, TTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Transceiver Protocols PECL Number of transmitters 2 Number of receivers 2 Supply voltage (V) 5 Signaling rate (MBits) 100 Input signal PECL, TTL Output signal PECL, TTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 16 59.4 mm² 9.9 x 6 SOIC (DW) 16 106.09 mm² 10.3 x 10.3
  • Functional Replacement for the Agere BTF1A
  • Driver Features
    • Third-State Logic Low Output
    • ESD Protection HBM > 3 kV, CDM > 2 kV
    • No Line Loading when VCC = 0
    • Capable of Driving 50- loads
    • 2.0-ns Maximum Propagation Delay
    • 0.2-ns Output Skew (typical)
  • Receiver Features
    • High-Input Impedance Approximately 8 k
    • 4.0-ns Maximum Propagation Delay
    • 50-mV Hysteresis
    • Slew Rate Limited (1 ns min 80% to 20%)
    • ESD Protection HBM > 3 kV, CDM > 2 kV
    • -1.1-V to 7.1-V Input Voltage Range
  • Common Device Features
    • Common Enable for Each Driver/Receiver Pair
    • Operating Temperature Range: -40°C to 85°C
    • Single 5.0 V ± 10% Supply
    • Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package

  • Functional Replacement for the Agere BTF1A
  • Driver Features
    • Third-State Logic Low Output
    • ESD Protection HBM > 3 kV, CDM > 2 kV
    • No Line Loading when VCC = 0
    • Capable of Driving 50- loads
    • 2.0-ns Maximum Propagation Delay
    • 0.2-ns Output Skew (typical)
  • Receiver Features
    • High-Input Impedance Approximately 8 k
    • 4.0-ns Maximum Propagation Delay
    • 50-mV Hysteresis
    • Slew Rate Limited (1 ns min 80% to 20%)
    • ESD Protection HBM > 3 kV, CDM > 2 kV
    • -1.1-V to 7.1-V Input Voltage Range
  • Common Device Features
    • Common Enable for Each Driver/Receiver Pair
    • Operating Temperature Range: -40°C to 85°C
    • Single 5.0 V ± 10% Supply
    • Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package

The TB5T1 device is a dual differential driver/receiver circuit that transmits and receives digital data over balanced transmission lines. The dual drivers translate input TTL logic levels to differential pseudo-ECL output levels. The dual receivers convert differential-input logic levels to TTL output levels. Each driver or receiver pair has its own common enable control allowing serial data and a control clock to be transmitted and received on a single integrated circuit. The TB5T1 requires the customer to supply termination resistors on the circuit board.

The power-down loading characteristics of the receiver input circuit are approximately 8 k relative to the power supplies; hence, it does not load the transmission line when the circuit is powered down.

In circuits with termination resistors, the line remains impedance- matched when the circuit is powered down. The driver does not load the line when it is powered down.

All devices are characterized for operation from -40°C to 85°C.

The logic inputs of this device include internal pull-up resistors of approximately 40 k that are connected to VCC to ensure a logical high level input if the inputs are open circuited.

The TB5T1 device is a dual differential driver/receiver circuit that transmits and receives digital data over balanced transmission lines. The dual drivers translate input TTL logic levels to differential pseudo-ECL output levels. The dual receivers convert differential-input logic levels to TTL output levels. Each driver or receiver pair has its own common enable control allowing serial data and a control clock to be transmitted and received on a single integrated circuit. The TB5T1 requires the customer to supply termination resistors on the circuit board.

The power-down loading characteristics of the receiver input circuit are approximately 8 k relative to the power supplies; hence, it does not load the transmission line when the circuit is powered down.

In circuits with termination resistors, the line remains impedance- matched when the circuit is powered down. The driver does not load the line when it is powered down.

All devices are characterized for operation from -40°C to 85°C.

The logic inputs of this device include internal pull-up resistors of approximately 40 k that are connected to VCC to ensure a logical high level input if the inputs are open circuited.

下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 1
類型 標題 日期
* Data sheet TB5T1, Dual Differential PECL Driver/Receiver datasheet (Rev. C) 2007年 10月 23日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

TB5T1DW IBIS Model

SLLC205.ZIP (15 KB) - IBIS Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
封裝 引腳 下載
SOIC (D) 16 檢視選項
SOIC (DW) 16 檢視選項

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 資格摘要
  • 進行中可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片