封裝資訊
| 封裝 | 引腳 SOT-23 (DBV) | 5 |
| 作業溫度範圍 (°C) -40 to 125 |
| 包裝數量 | 運送包裝 3,000 | LARGE T&R |
TPS3840 的特色
- Wide operating voltage: 1.5 V to 10 V
- Nano supply current: 300 nA
(Typ), 700 nA (Max)
- Fixed threshold voltage
(VIT-)
- Threshold from 1.6 V to 4.9 V in 0.1-V steps
- High accuracy: 1% (Typ), 1.5% (Max)
- Built-in hysteresis
(VIT+)
- 1.6 V < VIT- ≤ 3.0 V = 100 mV (Typical)
- 3.1 V ≤ VIT- < 4.9 V = 200 mV (Typical)
- Start-up delay
(tSTRT): 220 µs (Typ), 350 µs (Max)
- Programmable reset time delay
(tD):
- 50 µs (no capacitor) to 6.2 s (10-µF)
- Active-low manual reset (MR)
- Three output topologies:
- TPS3840DL: open-drain, active-low (RESET), requires pull-up resistor
- TPS3840PL: push-pull, active-low (RESET)
- TPS3840PH: push-pull, active-high (RESET)
- Wide temperature range: –40°C to +125°C
- Package: SOT23-5 (DBV)
TPS3840 的說明
Wide Vin allows monitoring 9V rails or batteries without external components and 24V rails with external resistors. Nano-Iq extends battery life for low power applications and minimizes current consumption when using external resistors. Fast start-up delay allows the detection of a voltage fault before the rest of the system powers up providing maximum safety in hazardous start-up fault conditions. Low Power-on-Reset (VPOR) prevents false resets, premature enable or turn-on of next device, and proper transistor control during power-up and power-down.
Reset output signal is asserted when the voltage at VDD drops below the negative voltage threshold (VIT-) or when manual reset (MR) is pulled to a low logic (VMR_L). Reset signal is cleared when VDD rise above VIT- plus hysteresis (VIT+) and manual reset is floating or above VMR_H and the reset time delay (tD) expires. Reset time delay can be programmed by connecting a capacitor between CT pin and ground. For a fast reset CT pin can be left floating.
Additional features: Built-in glitch immunity protection for MR and VDD, built-in hysteresis, low open-drain output leakage current (ILKG(OD)).