TRF3761-C
- Fully Integrated VCO
- Low Phase Noise: –137dBc/Hz (at 600kHz, fVCO
of 1.9GHz) - Low Noise Floor: –158dBc/Hz at 10MHz Offset
- Integer-N PLL
- Input Reference Frequency range: 10MHz to
104MHz - VCO Frequency Divided by 2-4 Output
- Output Buffer Enable Pin
- Programmable Charge Pump Current
- Hardware and Software Power Down
- 3-Wire Serial Interface
- Single Supply: 4.5V to 5.25V Operation
TRF3761 is a family of high performance, highly integrated frequency synthesizers, optimized for high performance applications. The TRF3761 includes a low-noise, voltage-controlled oscillator (VCO) and an integer-N PLL.
TRF3761 integrates divide-by 1, 2, or 4 options for a more flexible output frequency range. It is controlled through a 3-wire serial-programming-interface (SPI) interface. For power sensitive applications the TRF3761 can be powered down by the SPI interface or externally via chip_en pin 2.
技術文件
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | TRF3761-x Integer-N PLL with Integrated VCO datasheet (Rev. K) | PDF | HTML | 2015/12/31 | ||
| 應用說明 | TRF3761 QFN Installation Using a Hakko Hot Air Rework Station | 2007/4/7 | ||||
| 應用說明 | Fractional/Integer-N PLL Basics | 1998/5/13 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發模組 (EVM) 的 GUI
SLWC102 — TRF3761EVM Software Package
計算工具
RF-CASCADE-CALC-TOOL — TI RF 級聯計算機
A browser-based RF lineup analysis tool supporting up to 10 stages. Computes gain, NF, OIP3, OIP2, OP1dB, and derived metrics. Features dual-axis Plotly charts, P1dB saturation detection, and export to CSV
計算工具
TRF3761CALC — TRF3761 Loop Filter Calculator
TRF3761CALC is a loop filter design tool for the TRF3761 PLL Frequency Synthesizer with integrated VCO.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RHA) | 40 | Ultra Librarian |