VSP5621
- Four-Channel CCD/CMOS Signal: 2-Channel,
3-Channel, and 4-Channel Selectable - Power Supply: 3.3 V Only, Typ
(Built-in LDO, 3.3 V to 1.8 V) - Maximum Conversion Rate:
- VSP5620: 35 MSPS
- VSP5621: 50 MSPS
- VSP5622: 70 MSPS
- 16-Bit Resolution
- CDS/SH Selectable
- Maximum Input Signal Range: 2.0 V
- Analog and Digital Hybrid Gain:
- Analog Gain: 0.5 V/V to 3.5 V/V in
3/64-V/V Steps - Digital Gain: 1 V/V to 2 V/V in
1/256-V/V Steps
- Analog Gain: 0.5 V/V to 3.5 V/V in
- Offset Correction DAC: ±250 mV, 8-Bit
- Standard LVDS/CMOS Selectable Output:
- LVDS:
- Data Channel: 2-Channel
- Clock Channel: 1-Channel
- 8-Bit/7-Bit Serializer Selectable
- CMOS: 4 Bits × 4
- LVDS:
- Timing Generator
- Fast Transfer Clock: One Signal
- Slow Transfer Clock: One Signal
- LED Driver: Three Channels
- Current: 60-mA/Channel Max,
16-Steps/Channel
- Current: 60-mA/Channel Max,
- Timing Adjustment Resolution: tMCLK/48
- Input Clamp/Input Reference Level Internal/
External Selectable - Reference DAC: 0.5 V, 1.1 V, 1.5 V, 2 V
- SPI: Three-Wire Serial
- GPIO: Four-Port
- Power (at 4-channel, LVDS, 3.3 V, without LED Driver):
- VSP5620: 320 mW at 35 MSPS
- VSP5621: 406 mW at 50 MSPS
- VSP5622: 523 mW at 70 MSPS
The VSP5620/21/22 are high-speed, high-performance, 16-bit analog-to-digital-converters (ADCs) that have four independent sampling circuit channels for multi-output charge-coupled device (CCD) and complementary metal oxide semiconductor (CMOS) line sensors. Pixel data from the sensor are sampled by the sample/hold (SH) or correlated double sampler (CDS) circuit, and are then converted to digital data by an ADC. Data output is selectable in low-voltage differential signaling (LVDS) or CMOS modes.
The VSP5620/21/22 include a programmable gain to support the pixel level inflection caused by luminance and a built-in light-emitting diode (LED) driver to adjust the brightness. The integrated digital-to-analog-converter (DAC) can be used to adjust the offset level for the analog input signal. Furthermore, the timing generator (TG) is integrated in these devices for the control of sensor operation.
The VSP5620/21/22 use 1.65 V to 1.95 V for the core voltage and 3.0 V to 3.6 V for I/Os. The core voltage is supplied by a built-in low-dropout regulator (LDO).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 16-Bit, 4-Channel, CCD/CMOS Sensor AFE with LED Driver datasheet (Rev. A) | 2014/5/22 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RSL) | 48 | Ultra Librarian |