AFE7769EVM

AFE7769 quad-channel RF transceiver evaluation module

AFE7769EVM

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Overview

The AFE7769 evaluation module (EVM) is a board used to evaluate the AFE77xx family of integrated RF transceivers. AFE77xx devices support up to four-transmit, four-receive, and two feedback channels (4T4R2F) and integrate phase-locked loops (PLLs) and voltage-controlled oscillators (VCOs) for generation of data-converter clocks and LO, with LO frequency tunable from 600 MHz to 6 GHz.

This standard EVM incorporates RF baluns to specifically support 600 MHz to 2700 MHz. The AFE77xx device integrates eight JESD204B/C-compatible serializer/deserializer (SerDes) transceivers capable of running up to 29.5 Gbps to transmit and receive digital data through the onboard FMC connector.

AFE7769EVM includes the LMK04828 clock generator for providing reference clocks and sysref to the AFE and capture card (FPGA). The EVM works off a single 6-V input and includes complete power management. External clocking options include support for feeding the reference clock (for on-chip PLL) or the channel frequency (at 2x LO).

The design interfaces with TI pattern/capture card solutions (TSW14J56EVM and TSW14J57EVM, sold separately), as well as many FPGA development kits.

  • Evaluates AFE77xx integrated transceiver family of devices
  • Simplified digital interface with JESD204B/C; supports up to 29.5-Gbps lane rates
  • JESD subclass 1 for multiple-device synchronization
  • Onboard clocking solution with optional external feed
  • Onboard power-management scheme

  • AFE7769 evaluation module
  • USB cable
  • Power cable

RF-sampling transceivers
AFE7769 Quad-channel RF transceiver with dual feedback paths and four PLLs AFE7799 Quad-channel RF transceiver with dual feedback paths

 

Clock jitter cleaners & synchronizers
LMK04828 Ultra-low jitter synthesizer & jitter cleaner
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Important note

AFE7769EVM user's guide is available. Request now

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Evaluation board

AFE7769EVM – AFE7769 quad-channel RF transceiver evaluation module

TI's Standard Terms and Conditions for Evaluation Items apply.

Design files

AFE7769EVM Design Package SBAC252.ZIP (12488 KB)

Technical documentation

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Type Title Date
More literature AFE7769EVM EU Declaration of Conformity (DoC) May 20, 2019

Related design resources

Hardware development

EVALUATION BOARD
TSW14J56EVMData capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-12.5Gbps
TSW14J57EVMData capture/pattern generator: data converter EVM with 16 JESD204B lanes from 1.6-15Gbps

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