Data capture/pattern generator: data converter EVM with 16 JESD204B/C lanes from 1.6 to 24.5 Gbps


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The TSW14J58 evaluation module (EVM) is a next-generation data capture card used to evaluate the performance of the TI JESD204B/C family of high-speed analog-to-digital converters (ADCs), high-speed digital-to-analog converters (DACs), and analog front ends (AFEs).

Populated with a Xilinx® Kintex™ UltraScale+™ field programmable gate array (FPGA) and using JESD204B/C IP solutions, TSW14J58EVM can be dynamically configured to support all lane speeds from 1.6 Gbps to 24.5 Gbps, from 1 to 16 lanes.

Together with high-speed data converter pro software (DATACONVERTERPRO-SW), TSW14J58EVM is a complete system that captures and evaluates data samples from ADC, DAC and AFE EVMs that use JESD204B and/or JESD204C.

If your application does not require lane rates higher than 15 Gbps, consider using TSW14J56EVM for maximum lane rates up to 12.5 Gbps or TSW14J57EVM for maximum lane rates up to 15 Gbps.

  • Quickly evaluate JESD204B and JESD204C ADC, DAC or AFE performance using DATACONVERTERPRO-SW
  • Direct connection to all TI JESD204B and JESD204C EVMs using an FPGA mezzanine card (FMC+) standard connector (backwards compatible to FMC-equipped EVMs)
  • JESD204B and JESD204C receive (RX) and transmit (TX) IP cores with 16 routed transceiver channels; operating range from 1.6 Gbps to 24.5 Gbps
  • Support for SUBCLASS 0, 1 and 2 operation
  • Onboard high-speed USB 3.0-to-parallel converter bridges the FPGA interface to the host PC and GUI
  • 24-Gb DDR4 SDRAM (split into two banks each of three independent 256 × 16, 4-Gb SDRAMs; total of 1.5-G 16-bit samples)

  • TSW14J38 evaluation module
  • USB cable
  • Power cable

High-speed ADCs (>10MSPS)
ADC12DJ3200 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) ADC12DJ5200RF RF-sampling 12-bit ADC with dual-channel 5.2 GSPS or single-channel 10.4 GSPS ADC12QJ1600 Quad-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface and integrated sample clock generator


RF-sampling transceivers
AFE8092 Octal-channel RF transceiver

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Evaluation board

TSW14J58EVM – Data capture/pattern generator: data converter EVM with 16 JESD204B/C lanes from 1.6 to 24.5 Gbps


INI file for TSW14J58EVM – SLWC118.ZIP (1KB)

TI's Standard Terms and Conditions for Evaluation Items apply.

Design files

TSW14J58EVM Design Files SLWC119.ZIP (11561 KB)

Technical documentation

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Type Title Date
* User guide TSW14J58EVM JESD204C Data Capture and Pattern Generator Card User's Guide Mar. 08, 2021
Certificate TSW14J58EVM EU RoHS Declaration of Conformity (DoC) Mar. 16, 2021
More literature INI file for TSW14J58EVM Sep. 02, 2020
User guide High-Speed Data Converter Pro GUI User's Guide (Rev. D) Mar. 16, 2017

Related design resources

Software development

DATACONVERTERPRO-SW High-speed data converter pro software

Support & training

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