Product details

Applications Wireless infrastructure Number of TXs and RXs 4 TX, 4 RX, 2 F RF frequency (max) (MHz) 6000 RF frequency (min) (MHz) 600 Number of DUCs per TX 1 Number of DDCs per RX 1 Operating temperature range (°C) -40 to 85 Rating Catalog
Applications Wireless infrastructure Number of TXs and RXs 4 TX, 4 RX, 2 F RF frequency (max) (MHz) 6000 RF frequency (min) (MHz) 600 Number of DUCs per TX 1 Number of DDCs per RX 1 Operating temperature range (°C) -40 to 85 Rating Catalog
FCBGA (ABJ) 400 289 mm² 17 x 17
  • Quad transmitters based on direct up-conversion architecture:
    • Up to 600 MHz of RF transmitted bandwidth per chain
  • Quad receivers based on 0-IF down-conversion architecture:
    • Up to 200 MHz of RF received bandwidth per chain
  • Feedback chain based on RF sampling ADC:
    • Up to 600 MHz of RF received bandwidth
  • RF frequency range: 600 MHz to 6 GHz
  • Four wideband fractional-N PLL, VCO for TX and RX LO
  • Dedicated integer-N PLL, VCO for data converters clock generation
  • JESD204B and JESD204C SerDes interface support:
    • 8 SerDes transceivers up to 29.5 Gbps
    • 8b/10b and 64b/66b encoding
    • 16-bit, 12-bit, 24-bit and 32-bit formatting
    • Subclass 1 multi-device synchronization
  • Package: 17-mm × 17-mm FCBGA, 0.8-mm pitch
  • Quad transmitters based on direct up-conversion architecture:
    • Up to 600 MHz of RF transmitted bandwidth per chain
  • Quad receivers based on 0-IF down-conversion architecture:
    • Up to 200 MHz of RF received bandwidth per chain
  • Feedback chain based on RF sampling ADC:
    • Up to 600 MHz of RF received bandwidth
  • RF frequency range: 600 MHz to 6 GHz
  • Four wideband fractional-N PLL, VCO for TX and RX LO
  • Dedicated integer-N PLL, VCO for data converters clock generation
  • JESD204B and JESD204C SerDes interface support:
    • 8 SerDes transceivers up to 29.5 Gbps
    • 8b/10b and 64b/66b encoding
    • 16-bit, 12-bit, 24-bit and 32-bit formatting
    • Subclass 1 multi-device synchronization
  • Package: 17-mm × 17-mm FCBGA, 0.8-mm pitch

The AFE7769 device is a high-performance, multichannel transceiver, integrating four direct up-conversion transmitter chains, four direct down-conversion receiver chains, and two wideband RF sampling digitizing auxiliary chains (feedback paths). The high dynamic range of the transmitter and receiver chains enables wireless base stations to generate and receive 2G, 3G, 4G, and 5G signals.

The low power dissipation and large channel integration of the AFE7769 allows the device to address the power and size constraints of 4G and 5G massive MIMO base stations. The wideband and high dynamic range feedback path can assist the Digital Pre-Distortion (DPD) of the power amplifiers in the transmitter chain. The fast SerDes speed can help reduce the number of lanes required to transfer the data in and out.

Each receiver chain of the AFE7769 includes a 28-dB range digital step attenuator (DSA), followed by a wideband passive IQ demodulator, and a baseband amplifier with integrated programmable antialiasing low pass filters, driving a continuous-time sigma-delta ADC. The RX chain can receive an instantaneous bandwidth (IBW) up to 200 MHz. Each receiver channel has two analog peak power detectors and various digital power detectors to assist an external or internal autonomous AGC control for receiver channels, and a RF overload detector for device reliability protection. The integrated QMC (quadrature mismatch compensation) algorithm is capable to continuously monitor and correct for the RX chain I and Q imbalance mismatch without the need to inject any specific signals or perform offline calibration.

Each transmitter chain includes two 14-bit, 3-Gsps IQ DACs, followed by a programmable reconstruction and DAC image rejection filter, an IQ modulator driving a wideband RF amplifier with 39-dB range gain control. The TX chain integrated QMC and LO leakage cancellation algorithms, leveraging the FB path can constantly track and correct for the TX chain IQ mismatch and LO leakage.

Each FB path is based on RF sampling architecture, and includes an input RF DSA driving a 14-bit, 3-Gsps RF ADC. The direct sampling architecture provides an inherently wideband receiver chain and simplifies the calibration of the TX chains impairments. The FB path integrates two independent NCO that allows a fast switching between two observed RF input bands.

The synthesizer section integrates four fractional-N RF PLL that can generate four different RF LO, allowing the device to support up to two different bands, each one configured as two transmitters, two receivers and one feedback paths.

The AFE7769 device is a high-performance, multichannel transceiver, integrating four direct up-conversion transmitter chains, four direct down-conversion receiver chains, and two wideband RF sampling digitizing auxiliary chains (feedback paths). The high dynamic range of the transmitter and receiver chains enables wireless base stations to generate and receive 2G, 3G, 4G, and 5G signals.

The low power dissipation and large channel integration of the AFE7769 allows the device to address the power and size constraints of 4G and 5G massive MIMO base stations. The wideband and high dynamic range feedback path can assist the Digital Pre-Distortion (DPD) of the power amplifiers in the transmitter chain. The fast SerDes speed can help reduce the number of lanes required to transfer the data in and out.

Each receiver chain of the AFE7769 includes a 28-dB range digital step attenuator (DSA), followed by a wideband passive IQ demodulator, and a baseband amplifier with integrated programmable antialiasing low pass filters, driving a continuous-time sigma-delta ADC. The RX chain can receive an instantaneous bandwidth (IBW) up to 200 MHz. Each receiver channel has two analog peak power detectors and various digital power detectors to assist an external or internal autonomous AGC control for receiver channels, and a RF overload detector for device reliability protection. The integrated QMC (quadrature mismatch compensation) algorithm is capable to continuously monitor and correct for the RX chain I and Q imbalance mismatch without the need to inject any specific signals or perform offline calibration.

Each transmitter chain includes two 14-bit, 3-Gsps IQ DACs, followed by a programmable reconstruction and DAC image rejection filter, an IQ modulator driving a wideband RF amplifier with 39-dB range gain control. The TX chain integrated QMC and LO leakage cancellation algorithms, leveraging the FB path can constantly track and correct for the TX chain IQ mismatch and LO leakage.

Each FB path is based on RF sampling architecture, and includes an input RF DSA driving a 14-bit, 3-Gsps RF ADC. The direct sampling architecture provides an inherently wideband receiver chain and simplifies the calibration of the TX chains impairments. The FB path integrates two independent NCO that allows a fast switching between two observed RF input bands.

The synthesizer section integrates four fractional-N RF PLL that can generate four different RF LO, allowing the device to support up to two different bands, each one configured as two transmitters, two receivers and one feedback paths.

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For all other applications, see our general-purpose RF-sampling AFEs.

Technical documentation

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* Data sheet AFE7769 Quad-Channel RF Transceiver With Feedback Path datasheet PDF | HTML 08 Aug 2019
User guide Interfacing AFE7769DEVM With the Hitek Agilex eSOM7 FPGA PDF | HTML 28 Sep 2023
Application note Using AFE77xx in a Digital Pre-distortion System (Rev. B) 02 Sep 2021
Application note System Design Considerations when Upgrading from JESD204B to JESD204C (Rev. A) 05 Apr 2021
Application note Time Division Duplexing (TDD) in AFE77xx Integrated Transceiver (Rev. A) 05 Apr 2021
Application note AFE76xx, AFE77xx, and AFE79xx JESD204 Layer Testing 15 Apr 2020
User guide AFE77xx Latte GUI 25 Jul 2019
Application note Temp Profile to Maintain Optimum FIT Performance 23 Jul 2019
Application note Controlling Latte GUI from Python 08 Jul 2019
Application note AFE77xx Power Solutions 25 Jun 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

AFE7769-3P5EVM — AFE7769 quad-channel RF transceiver evaluation module with 3.5-GHz support

The AFE7769-3P5 evaluation module (EVM) is a board used to evaluate the AFE77xx family of integrated RF transceivers. AFE7769 and AFE7799 devices support up to four-transmit, four-receive, and two feedback channels (4T4R2F) and integrate phase-locked loops (PLLs) and voltage-controlled (...)

Not available on TI.com
Evaluation board

AFE7769EVM — AFE7769 quad-channel RF transceiver evaluation module

The AFE7769 evaluation module (EVM) is a board used to evaluate the AFE77xx family of integrated RF transceivers. AFE77xx devices support up to four-transmit, four-receive, and two feedback channels (4T4R2F) and integrate phase-locked loops (PLLs) and voltage-controlled oscillators (VCOs) for (...)

Not available on TI.com
Evaluation board

HTK-3P-AGILEX-ESOM7 — HITEK Agilex eSOM7 with FMC+ connector to RF transceiver EVMs

Hitek Systems' embedded System On Module (SOM) featuring Altera's Agilex 7 FPGA and TI's wireless infrastructure transceivers function as a quick evaluation and prototyping platform for 5G wireless solutions such as macro cell, repeater, and massive MIMO applications. This development platform is (...)

User guide: PDF | HTML
Evaluation board

ULTICHIP-3P-UC1046 — Ultichip Communication Technology small cell solutions based on UC1046 and AFE7769

The Ultichip Communication Technology Blade40 is a low-cost, high-performance Pico RU solution based on Ultichip's UC1046 digital front-end (DFE) and TI's AFE7769 transceiver, supporting 4G LTE, 5G NR or 4G/5G dual mode. The output power of Blade40 is up to 250 mW per antenna. Other configurations (...)

Driver or library

AFE77XX-WI-DESIGN AFE77xx Wireless Infrastructure (WI) design files

Secure Server Folder for all AFE77xx Devices
Supported products & hardware

Supported products & hardware

Firmware

TI204C-IP Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

Supported products & hardware

Supported products & hardware

GUI for evaluation module (EVM)

DATACONVERTERPRO-SW High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

Supported products & hardware

Supported products & hardware

Package Pins CAD symbols, footprints & 3D models
FCBGA (ABJ) 400 Ultra Librarian

Ordering & quality

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