AFE7769

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Quad-channel RF transceiver with dual feedback paths and four PLLs

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Product details

Parameters

# of TX/RX 4T4R2F Data rate (MSPS) 737 Operating temperature range (C) -40 to 85 Applications Wireless infrastructure open-in-new Find other RF-sampling transceivers

Package | Pins | Size

FCBGA (ABJ) 400 289 mm² 17 x 17 open-in-new Find other RF-sampling transceivers

Features

  • Quad transmitters based on direct up-conversion architecture:
    • Up to 600 MHz of RF transmitted bandwidth per chain
  • Quad receivers based on 0-IF down-conversion architecture:
    • Up to 200 MHz of RF received bandwidth per chain
  • Feedback chain based on RF sampling ADC:
    • Up to 600 MHz of RF received bandwidth
  • RF frequency range: 600 MHz to 6 GHz
  • Four wideband fractional-N PLL, VCO for TX and RX LO
  • Dedicated integer-N PLL, VCO for data converters clock generation
  • JESD204B and JESD204C SerDes interface support:
    • 8 SerDes transceivers up to 29.5 Gbps
    • 8b/10b and 64b/66b encoding
    • 16-bit, 12-bit, 24-bit and 32-bit formatting
    • Subclass 1 multi-device synchronization
  • Package: 17-mm × 17-mm FCBGA, 0.8-mm pitch

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Description

The AFE7769 device is a high-performance, multichannel transceiver, integrating four direct up-conversion transmitter chains, four direct down-conversion receiver chains, and two wideband RF sampling digitizing auxiliary chains (feedback paths). The high dynamic range of the transmitter and receiver chains enables wireless base stations to generate and receive 2G, 3G, 4G, and 5G signals.

The low power dissipation and large channel integration of the AFE7769 allows the device to address the power and size constraints of 4G and 5G massive MIMO base stations. The wideband and high dynamic range feedback path can assist the Digital Pre-Distortion (DPD) of the power amplifiers in the transmitter chain. The fast SerDes speed can help reduce the number of lanes required to transfer the data in and out.

Each receiver chain of the AFE7769 includes a 28-dB range digital step attenuator (DSA), followed by a wideband passive IQ demodulator, and a baseband amplifier with integrated programmable antialiasing low pass filters, driving a continuous-time sigma-delta ADC. The RX chain can receive an instantaneous bandwidth (IBW) up to 200 MHz. Each receiver channel has two analog peak power detectors and various digital power detectors to assist an external or internal autonomous AGC control for receiver channels, and a RF overload detector for device reliability protection. The integrated QMC (quadrature mismatch compensation) algorithm is capable to continuously monitor and correct for the RX chain I and Q imbalance mismatch without the need to inject any specific signals or perform offline calibration.

Each transmitter chain includes two 14-bit, 3-Gsps IQ DACs, followed by a programmable reconstruction and DAC image rejection filter, an IQ modulator driving a wideband RF amplifier with 39-dB range gain control. The TX chain integrated QMC and LO leakage cancellation algorithms, leveraging the FB path can constantly track and correct for the TX chain IQ mismatch and LO leakage.

Each FB path is based on RF sampling architecture, and includes an input RF DSA driving a 14-bit, 3-Gsps RF ADC. The direct sampling architecture provides an inherently wideband receiver chain and simplifies the calibration of the TX chains impairments. The FB path integrates two independent NCO that allows a fast switching between two observed RF input bands.

The synthesizer section integrates four fractional-N RF PLL that can generate four different RF LO, allowing the device to support up to two different bands, each one configured as two transmitters, two receivers and one feedback paths.

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For all other applications, see our general-purpose RF-sampling AFEs.

Technical documentation

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No results found. Please clear your search and try again. View all 13
Type Title Date
* Datasheet AFE7769 Quad-Channel RF Transceiver With Feedback Path datasheet Aug. 08, 2019
Application note AFE76xx, AFE77xx, and AFE79xx JESD204 Layer Testing Apr. 15, 2020
Technical articles So, what's a VNA anyway? Aug. 23, 2019
Technical articles So, what's the deal with frequency response? Aug. 23, 2019
Application note System Design Considerations when Upgrading from JESD204B to JESD204C Aug. 01, 2019
User guide AFE77xx Latte GUI Jul. 25, 2019
Application note Temp Profile to Maintain Optimum FIT Performance Jul. 23, 2019
Application note Controlling Latte GUI from Python Jul. 08, 2019
Application note Using AFE77xx in a Digital Pre-distortion System (Rev. A) Jul. 08, 2019
Application note AFE77xx Power Solutions Jun. 25, 2019
Application note Time Division Duplexing (TDD) in AFE77xx Integrated Transceiver Jun. 24, 2019
Technical articles So, what are S-parameters anyway? May 23, 2019
Technical articles How to achieve fast frequency hopping Mar. 03, 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
1999
Description

The AFE7769-3P5 evaluation module (EVM) is a board used to evaluate the AFE77xx family of integrated RF transceivers. AFE7769 and AFE7799 devices support up to four-transmit, four-receive, and two feedback channels (4T4R2F) and integrate phase-locked loops (PLLs) and voltage-controlled (...)

Features
  • Evaluates AFE77xx integrated transceiver family of devices
  • Simplified digital interface with JESD204B/C; supports up to 29.5-Gbps lane rates
  • JESD subclass 1 for multiple-device synchronization
  • Onboard clocking solution with optional external feed
  • Onboard power-management scheme
EVALUATION BOARD Download
1999
Description

The AFE7769 evaluation module (EVM) is a board used to evaluate the AFE77xx family of integrated RF transceivers. AFE77xx devices support up to four-transmit, four-receive, and two feedback channels (4T4R2F) and integrate phase-locked loops (PLLs) and voltage-controlled oscillators (VCOs) for (...)

Features
  • Evaluates AFE77xx integrated transceiver family of devices
  • Simplified digital interface with JESD204B/C; supports up to 29.5-Gbps lane rates
  • JESD subclass 1 for multiple-device synchronization
  • Onboard clocking solution with optional external feed
  • Onboard power-management scheme

Software development

FIRMWARE Download
JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
TI-JESD204-IP The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Features
  • Compatible with JEDEC JESD204a/b/c protocols
  • Supports subclass 1 deterministic latency and multidevice synchronization
  • Supported lane rates
    • Up to 16.375 Gbps in 8b/10b mode
    • Up to 20 Gbps in 64b/66b mode
  • Supports all protocol related error detection and reporting features
  • Integrated transport layer (...)

CAD/CAE symbols

Package Pins Download
FCBGA (ABJ) 400 View options

Ordering & quality

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