The Artix 7 power management reference design board uses power modules, linear regulators, and a PMBus compliant system controller to supply all required core and auxiliary voltages needed by the FPGA, including DDR memory termination. A Digital Power graphical user interface is used to monitor the voltage and current levels of the board’s power rails.
- Design optimized to support a 12V input
- 2 PMBus controllers monitors a total of 9 voltage rails
- Solution contains power modules providing up to 6A output current
- Low-noise LDOs provide power for transcievers
- DDR Memory provides volatile synchronous dynamic random access memory to store user code and data
- Design has been built and tested. Reference board is available from Xilinx