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Product details

Parameters

DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3 Control mode D-CAP, S3, S4/S5 Iout VTT (Max) (A) 3 Iq (Typ) (mA) 0.5 Output VREF, VTT Vin (Min) (V) 1.1 Vin (Max) (V) 3.5 Features S3/S5 Support Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other DDR memory power ICs

Package | Pins | Size

VSON (DRC) 10 9 mm² 3.00 x 3.00 VSON (DRC) 10 9 mm² 3 x 3 open-in-new Find other DDR memory power ICs

Features

  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink and Source Termination Regulator Includes Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF (Typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft Start, UVLO, and OCL
  • Thermal Shutdown
  • Supports DDR, DDR2, DDR3, DDR3L, Low-Power DDR3, and DDR4 VTT Applications
  • 10-Pin VSON Package With Thermal Pad

All trademarks are the property of their respective owners.

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Description

The TPS51200 device is a sink and source double data rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The TPS51200 maintains a fast transient response and requires a minimum output capacitance of only 20 µF. The TPS51200 supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT bus termination.

In addition, the TPS51200 provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The TPS51200 is available in the thermally efficient 10-pin VSON thermal pad package, and is rated both Green and Pb-free. It is specified from –40°C to +85°C.

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Technical documentation

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Type Title Date
* Datasheet TPS51200 Sink and Source DDR Termination Regulator datasheet (Rev. D) Mar. 19, 2020
Application notes Non-isolated point-of-load solutions for VR13.HC in rack server & datacenter app Mar. 05, 2019
Application notes DDR VTT Power Solutions: A Competitive Analysis Apr. 27, 2018
Application notes LDO Noise Demystified (Rev. A) Aug. 09, 2017
Application notes LDO PSRR Measurement Simplified (Rev. A) Aug. 09, 2017
Selection guides TI Components for Aerospace and Defense Guide (Rev. E) Mar. 22, 2017
User guides TI Power Reference Design for Xilinx(R) Virtex(R)-7 (VC709) (Rev. A) Dec. 16, 2014
User guides TI Power Reference Design for Xilinx® Kintex®-7 (KC705) (Rev. A) Dec. 16, 2014
User guides TI Power Reference Design for Xilinx® Zynq 7000 (ZC702) (Rev. A) Dec. 16, 2014
Technical articles A New Understanding: Blast Motion redefines movement, tracking and training for athletes. Aug. 06, 2014
Technical articles Improving Fly-Buck Regulation Using Opto (Part-1) Jul. 15, 2014
Technical articles Altium and WEBENCH – together at last Jul. 12, 2014
Technical articles Using telemetry in point-of-load applications Jun. 24, 2014
User guides PMP7977 Test Results (Rev. A) Jun. 11, 2014
Selection guides Power, Interface and Clock Solutions for the TED Spartan-6 FPGA (Rev. A) May 29, 2014
User guides TI Power Reference Design for Xilinx® Artix®-7 (AC701) May 12, 2014
User guides PMP7977 User's Guide Sep. 11, 2013
Selection guides Power, Interface and Switch Solutions for Micron Memory (Rev. A) Jun. 18, 2013
More literature Computing DDR DC-DC Power Solutions Aug. 22, 2012
Selection guides Power Management Solutions Set-Top Box and Digital TV (Rev. A) Apr. 18, 2012
More literature 2010 Intel™ Atom Power System EVM and Support Tools [WMV] Jul. 20, 2010
Application notes Power Ref Design for TMS320C6472, 12-Vin Digital Pwr Cntrlrs, and LDOs (Rev. A) May 24, 2010
Application notes Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs Apr. 28, 2010
Application notes Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices Apr. 20, 2010
Application notes Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) Mar. 31, 2010
Application notes 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) Mar. 26, 2010
Application notes Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs Mar. 26, 2010
Application notes TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers Mar. 26, 2010
White papers Spartan 6 LX150T Modular Solution Oct. 14, 2009
User guides Virtex 6 LX130T Module design Aug. 27, 2009
User guides Using the TPS51200 Evaluation Module May 28, 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
$1,146.54
Description
J6Entry, RSP and TDA2E-17 CPU Board EVM is an evaluation platform designed to speed up development efforts and reduce time to market for Infotainment  reconfigurable Digital Cluster or Integrated Digital Cockpit and ADAS applications. The CPU board integrates key peripherals such as parallel (...)
Features
  • 2GB DDR3L
  • LP8733/LP8732 Power Solution
  • On-board eMMC, NAND, NOR
  • USB3, USB2, PCIe, Ethernet, COM8Q, CAN, MLB, MicroSD and HDMI connectors
EVALUATION BOARDS Download
$2,324.44
Description

The J6Entry/RSP EVM is an evaluation platform designed to speed up development efforts and reduce time to market for applications such as Infotainment, reconfigurable Digital Cluster or Integrated Digital Cockpit.

The main CPU board integrates these key peripherals such as Ethernet or HDMI, while the (...)

Features
  • 10.1" Display with capacitive Touch
  • JAMR3 Radio Tuner Application Board
  • 2GB DDR3L
  • LP8733/LP8732 Power Solution
  • On-board eMMC, NAND, NOR
  • USB3, USB2, PCIe, Ethernet, COM8Q, CAN, MLB, MicroSD and HDMI connectors
EVALUATION BOARDS Download
document-generic User guide
$49.00
Description

The TPS51200EVM evaluation board, HPA322A is designed to evaluate the performance and characteristics of TI's cost optimized DDR/DDR2/DDR3/LP DDR3 VTT termination regulator, the TPS51200. The TPS51200 is designed to provide proper termination voltage and a 10-mA buffered reference voltage for DDR (...)

Features
  • Input Voltage: Support 2.5V Rail and 3.3V Rail
  • VLDOIN, VDDQ Voltage Range: 1.2V-2.5V
  • Build-in transient load switches (with both sinking and sourcing capability) to emulate the sink/source transient behavior which helps to evaluate the dynamic performance. For ease of use, both load step and timing of (...)
EVALUATION BOARDS Download
document-generic User guide
Description
What is BeagleBone® AI?

Built on the proven BeagleBoard.org® open source Linux approach, BeagleBone® AI fills the gap between small SBCs and more powerful industrial computers. Based on the Texas Instruments, Sitara™ AM5729 processor, developers have access to a highly integrated and (...)

Design tools & simulation

SIMULATION MODELS Download
SLUM148.TSC (127 KB) - TINA-TI Reference Design
SIMULATION MODELS Download
SLUM149.ZIP (18 KB) - TINA-TI Spice Model
SIMULATION MODELS Download
SLUM150.TSC (755 KB) - TINA-TI Reference Design
SIMULATION MODELS Download
SLUM151.ZIP (17 KB) - TINA-TI Spice Model
SIMULATION MODELS Download
SLVM068A.ZIP (38 KB) - PSpice Model
SIMULATION MODELS Download
SLVM069.ZIP (30 KB) - PSpice Model
BILL OF MATERIALS (BOM) Download
SLVR351.PDF (304 KB)
BILL OF MATERIALS (BOM) Download
SLVR352.PDF (334 KB)
BILL OF MATERIALS (BOM) Download
TIDR156A.PDF (595 KB)
PCB LAYOUTS Download
TIDU151.PDF (6781 KB)
SCHEMATICS Download
SLVR360.PDF (166 KB)
SCHEMATICS Download
TIDR155A.PDF (598 KB)

Reference designs

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TIDA-050034 TIDA-050034 is a fully functional development board combining a TI PMIC, TPS65218DO, with NXP i.MX 7Dual Application Processor.

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OPC UA Data Access Server for AM572x Reference Design
TIDEP0078 — OPC UA is an industrial machine-to-machine protocol designed to allow interoperability and communication between all machines connected under Industry 4.0. The TIDEP0078 TI Design demonstrates use of the MatrikonOPC™ OPC UA server development kit (SDK) to allow communications using an OPC UA (...)
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High efficiency power supply architecture reference design for protection relay processor module
TIDA-010011 — This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
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REFERENCE DESIGNS Download
Integrated Power Supply Reference Design for Xilinx Zynq® UltraScale+™ ZU2CG−ZU5EV MPSoCs
TIDA-01480 The TIDA-01480 reference design is a scalable power supply designed to provide power to the Xilinx Zynq UltraScale+ (ZU+) family of MPSoC devices. The design receives power from a standard DC power supply and provides power to all rails of the Xilinx chipset and DDR memory through a well-defined (...)
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REFERENCE DESIGNS Download
Integrated Power Supply Reference Design for Xilinx Artix®-7, Spartan®-7, and Zynq®-7000 FPGAs
TIDA-050000 This reference design is a scalable power supply designed to provide power to the Xilinx Artix-7, Spartan-7, and Zynq-7000 families of FPGA-based devices. The design receives power from a standard DC power supply and provides power to all rails of the Xilinx chipset and DDR memory through a (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
3D Machine Vision Reference Design Based on AM572x Processor with DLP® Structured Light
TIDEP0076 — The TIDEP0076 3D machine vision design describes an embedded 3D scanner based on the structured light principle. A digital camera along with a Sitara™ AM57xx processor System on Chip (SoC)  is used to capture reflected light patterns from a DLP4500-based projector. Subsquent processing of (...)
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REFERENCE DESIGNS Download
EMI/EMC Compliant Industrial Temp Dual Port Gigabit Ethernet PHY Reference Design
TIDA-00204 This design allows for performance evaluation of two industrial grade DP83867IR Gigabit Ethernet PHYs and Sitara™ host processors with integrated Ethernet MAC and Switch. It was developed to meet industrial requirements for EMI and EMC. The application firmware implements a driver for the PHY (...)
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Monte-Carlo Simulation on AM57x Using OpenCL for DSP Acceleration Reference Design
TIDEP0046 TI’s high performance ARM® Cortex®-A15 based AM57x processors also integrate C66x DSPs. These DSPs were designed to handle high signal and data processing tasks that are often required by industrial, automotive and financial applications. The AM57x OpenCL implementation makes it easy (...)
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Power and Thermal Design Considerations Using TI's AM57x Processor Reference Design
TIDEP0047 This TI Design (TIDEP0047) is a reference platform based on the AM57x processor and companion TPS659037 power management integrated circuit (PMIC).  This TI Design specifically highlights important power and thermal design considerations and techniques for systems designed with AM57x and (...)
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ARM MPU with Integrated BiSS C Master Interface Reference Design
TIDEP0022 Implementation of BiSS C Master protocol on Industrial Communication Sub-System (PRU-ICSS). The design provides full documentation and source code for Programmable Realtime Unit (PRU).
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ARM MPU with Integrated HIPERFACE DSL Master Interface Reference Design
TIDEP0035 Implementation of HIPERFACE DSL Master protocol on Industrial Communication Sub-System (PRU-ICSS). The two wire interface allows for integration of position feedback wires into motor cable.  Complete solution consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver reference design.
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EnDat 2.2 System Reference Design
TIDEP0050 The TIDEP0050 TI Design implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and (...)
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Parallel Redundancy Protocol (PRP) Ethernet Reference Design for Substation Automation
TIDEP0054 This TI Design implements a solution for high-reliability, low-latency network communications for substation automation equipment in Smart Grid transmission and distribution networks. It supports the Parallel Redundancy Protocol (PRP) specification in the IEC 62439 standard using the PRU-ICSS. This (...)
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Reference Design for Telecom Applications (.9V @ .5A)
PMP4742 PMP4742.1 comprises a negative input (-10.8V to -13.2V) to positive output (12V@1A average) inverting buck-boost converter with TPS40210; a hot swap circuit with TPS2420 quickly limits the output current to 2A peak.
Design files
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Power for Altera Cyclone V (Cyclone 5) FPGA (.75V@.75A) Reference Design
PMP8571 — PMP8571 is an easy to use power solution designed using integrated inductor power modules for Altera’s Cyclone 5 FPGA. This design used TPS84621 and TPS84320 along with TPS51200 to generate 5 rails to power the FPGA.
Design files
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Arria V Power Reference Design
PMP8610 Power Solution Reference Design for Arria V FPGA from Altera.  This solution uses integrated inductor modules for ease of use to help design power solution for Arria V FPGA from Altera.  This design incorporate sequencing need for the PFGA as well.

Special Note

Go to the TPS84 to LMZ3 part number cross (...)

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Design files
REFERENCE DESIGNS Download
Altera Cyclone V SoC Power Supply Reference Design
PMP9353 The PMP9353 reference design is a complete power solution for Altera Cyclone V SoC devices. This design uses several LMZ3 series modules , two LDOs, and a DDR termination regulator to provide all the necessary rails to power the SoC chip. This design also shows correct power-up sequencing.
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Altera Arria V FPGA Power Supply Reference Design
PMP9357 The PMP9357 reference design is a complete power solution for Altera's Arria V series FPGAs.  This design uses several TPS54620 synchronous step down converters, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA.  To provide correct power (...)
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Altera® Stratix® V FPGA Power Solution
PMP9365 The PMP9365 reference design provides all the power supply rails necessary to power Altera's Stratix V family of FPGAs.  This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA.  It also features two (...)
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Xilinx Artix 7 FPGA with PMBus Power Management Reference Design
PMP7977 The Artix 7 power management reference design board uses power modules, linear regulators, and a PMBus compliant system controller to supply all required core and auxiliary voltages needed by the FPGA, including DDR memory termination. A Digital Power graphical user interface is used to monitor the (...)
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Analog Solution for Kintex 7
PMP7978 — Xilinx chose TI as the power solution vendor to power Kintex 7 FPGA (along with other analog solution from TI). You will find Schematic and bill of material fo the solution Xilinx used on the development kits.
REFERENCE DESIGNS Download
Reference Design using TMS320C6657 to Implement Efficient OPUS Codec Solution
TIDEP0036 The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio (...)
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Power Reference Design for Xilinx® Zynq®-7000
PMP7877 The PMP7877 reference design provides all the rails necessary to power a Xilinx® Zynq®-7000 series SoC.  It operates from an input voltage range of 10.8Vin to 13.2Vin and has seven regulated outputs: 1Vout @ 5A, 1.8Vout @ 2.5A, 1.5Vout @ 6A, 3.3Vout @ 5A, 3.3Vout @ 5A, 5Vout @ 2A, and (...)
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Analog Solution for Virtex 7
PMP7976 — Xilinx chose TI as the power solution vendor to power Virtex 7 FPGA (along with other analog solution from TI). You will find Schematic and bill of material fo the solution Xilinx used on the development kits.
REFERENCE DESIGNS Download
Analog Solution for Zynq
PMP7975 — Xilinx chose TI as the power solution vendor to power Zynq FPGA (along with other analog solution from TI). You will find Schematic and bill of material fo the solution Xilinx used on the development kits.
REFERENCE DESIGNS Download
Altera Arria V GX FPGA Power Solution Reference Design
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