Product details

DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3 Control mode D-CAP, S3, S4/S5 Iout VTT (Max) (A) 3 Iq (Typ) (mA) 0.5 Output VREF, VTT Vin (Min) (V) 1.1 Vin (Max) (V) 3.5 Features S3/S5 Support Rating Catalog
DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3 Control mode D-CAP, S3, S4/S5 Iout VTT (Max) (A) 3 Iq (Typ) (mA) 0.5 Output VREF, VTT Vin (Min) (V) 1.1 Vin (Max) (V) 3.5 Features S3/S5 Support Rating Catalog
VSON (DRC) 10 9 mm² 3.00 x 3.00 VSON (DRC) 10 9 mm² 3 x 3 VSON (DRC) 10
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink and Source Termination Regulator Includes Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF (Typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft Start, UVLO, and OCL
  • Thermal Shutdown
  • Supports DDR, DDR2, DDR3, DDR3L, Low-Power DDR3, and DDR4 VTT Applications
  • 10-Pin VSON Package With Thermal Pad
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink and Source Termination Regulator Includes Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF (Typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft Start, UVLO, and OCL
  • Thermal Shutdown
  • Supports DDR, DDR2, DDR3, DDR3L, Low-Power DDR3, and DDR4 VTT Applications
  • 10-Pin VSON Package With Thermal Pad

The TPS51200 device is a sink and source double data rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The TPS51200 maintains a fast transient response and requires a minimum output capacitance of only 20 µF. The TPS51200 supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT bus termination.

In addition, the TPS51200 provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The TPS51200 is available in the thermally efficient 10-pin VSON thermal pad package, and is rated both Green and Pb-free. It is specified from –40°C to +85°C.

The TPS51200 device is a sink and source double data rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The TPS51200 maintains a fast transient response and requires a minimum output capacitance of only 20 µF. The TPS51200 supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT bus termination.

In addition, the TPS51200 provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The TPS51200 is available in the thermally efficient 10-pin VSON thermal pad package, and is rated both Green and Pb-free. It is specified from –40°C to +85°C.

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Technical documentation

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Type Title Date
* Data sheet TPS51200 Sink and Source DDR Termination Regulator datasheet (Rev. D) PDF | HTML 19 Mar 2020
Application note LDO Noise Demystified (Rev. B) PDF | HTML 18 Aug 2020
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 09 Jul 2020
Application note Point-of-Load Solutions for Data Center App Implementing VR13.HC Vccin Spec (Rev. A) PDF | HTML 08 Jan 2020
Selection guide Power Management Guide 2018 (Rev. R) 25 Jun 2018
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 09 Aug 2017
Test report TI Power Reference Design for Xilinx(R) Virtex(R)-7 (VC709) (Rev. A) 16 Dec 2014
Test report TI Power Reference Design for Xilinx® Kintex®-7 (KC705) (Rev. A) 16 Dec 2014
User guide TI Power Reference Design for Xilinx® Zynq 7000 (ZC702) (Rev. A) 16 Dec 2014
Test report PMP7977 Test Results (Rev. A) 11 Jun 2014
Test report TI Power Reference Design for Xilinx® Artix®-7 (AC701) 12 May 2014
User guide PMP7977 User's Guide 11 Sep 2013
More literature Computing DDR DC-DC Power Solutions 22 Aug 2012
Application note Power Ref Design for TMS320C6472, 12-Vin Digital Pwr Cntrlrs, and LDOs (Rev. A) 24 May 2010
Technical article Embedded Computers with TI Power in a myriad of applications 15 May 2010
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs 28 Apr 2010
Application note Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices 20 Apr 2010
Application note Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) 31 Mar 2010
Application note 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) 26 Mar 2010
Application note Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs 26 Mar 2010
Application note TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers 26 Mar 2010
White paper Spartan 6 LX150T Modular Solution 14 Oct 2009
User guide Virtex 6 LX130T Module design 27 Aug 2009
EVM User's guide Using the TPS51200 Evaluation Module 28 May 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TPS51200EVM — TPS51200 Sink Source DDR Termination Regulator

The TPS51200EVM evaluation board, HPA322A is designed to evaluate the performance andcharacteristics of TI's cost optimized DDR/DDR2/DDR3/LP DDR3 VTT termination regulator, the TPS51200. The TPS51200 is designed to provide proper termination voltage and a 10-mA buffered reference voltage for DDR (...)

Not available on TI.com
Simulation model

TPS51200 TINA-TI Start-Up Transient Reference Design

SLUM148.TSC (127 KB) - TINA-TI Reference Design
Simulation model

TPS51200 TINA-TI Transient Spice Model

SLUM149.ZIP (18 KB) - TINA-TI Spice Model
Simulation model

TPS51200 TINA-TI Average Reference Design

SLUM150.TSC (755 KB) - TINA-TI Reference Design
Simulation model

TPS51200 TINA-TI Average Spice Model

SLUM151.ZIP (17 KB) - TINA-TI Spice Model
Simulation model

TPS51200 PSpice Transient Model (Rev. A)

SLVM068A.ZIP (38 KB) - PSpice Model
Simulation model

TPS51200 PSpice Average Model

SLVM069.ZIP (30 KB) - PSpice Model
CAD/CAE symbol

TPS51200 Orcad Model

SLVC210.ZIP (1 KB)
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VSON (DRC) 10 View options

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