Analog Front-End Reference Design for Imaging Using Time-Interleaved SAR ADCs with 73dB SNR, 7.5MSPS


Design files


This reference design demonstrates how to achieve multiple ADC interleaving with high sampling rates and good resolution at low BOM-cost. The reference design was built with electronic imaging systems in mind. High definition imaging and other high speed signal processing applications require ADCs that can achieve high resolution, high SNR, high speed and low power consumption. These requirements cannot always be met with a  single chip. By interleaving multiple SAR ADCs, the design optimizes trade-offs between different ADCs in order to meet all of the system requirements.

  • Resolution: 14-bit
  • input type: unipolar single-ended
  • SNR > 73dB, ENOB: 12-bit, THD < -80dB
  • Power: < 33mW
  • Low latency compared to pipeline ADC-based solution
  • Small form factor: 22mm x 13mm
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUD58.PDF (1400 K)

Reference design overview and verified performance test data

TIDRS28.PDF (319 K)

Detailed schematic diagram for design layout and components

TIDRS29.PDF (98 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRS30.PDF (187 K)

Detailed overview of design layout for component placement

TIDRS33.ZIP (1756 K)

Files used for 3D models or 2D drawings of IC components


Design file that contains information on physical board layer of design PCB

TIDRS31.PDF (786 K)

PCB layer plot file used for generating PCB design layout

TIDRS32.PDF (235 K)

PCB layer plot file used for generating PCB design layout


Includes TI products in the design and potential alternatives.

High-speed op amps (GBW ≥ 50 MHz)

OPA836Very Low Power, Rail to Rail out, Negative Rail in, VFB Op Amp

Data sheet: PDF
Linear & low-dropout (LDO) regulators

LP5907250-mA, low-noise, high-PSRR, ultra-low-dropout voltage regulator with low IQ and enable

Data sheet: PDF | HTML
Noninverting buffers & drivers

SN74AUCH2448-ch, 0.8-V to 2.7-V high speed buffers with bus-hold and 3-state outputs

Data sheet: PDF
Precision ADCs

ADS705614-bit 2.5-MSPS ultra-low-power ultra-small-size SAR ADC with SPI

Data sheet: PDF | HTML
Series voltage references

REF20333.3-V Vref, low-drift, low-power, dual-output Vref & Vref/2 voltage reference

Data sheet: PDF | HTML

Technical documentation

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Type Title Date
* Design guide AFE Ref Design for Imaging Using Time-Interleaved SAR ADCs w/ 73dB SNR, 7.5 MSPS Aug. 07, 2017
Application note Low-Cost, Low-Power, Small 14-bit AFE: Interleaved ADCs Scalable up to 7.5 MSPS May 26, 2017

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